As a researcher focused on power electronics, I have devoted significant effort to investigating the operational challenges that photovoltaic (PV) systems face when connected to unbalanced utility grids. In my work, I have realized that most commercial solar inverters are designed under the assumption that the grid voltage is perfectly balanced. However, in practical distribution networks, single-phase loads, asymmetrical line impedances, lightning strikes, and switching operations frequently create unbalanced voltage conditions. When such imbalances occur, the performance of solar inverters degrades considerably: the DC-link voltage begins to oscillate at twice the fundamental frequency, the three-phase grid-connected currents become asymmetrical, and the total harmonic distortion (THD) increases sharply. In severe cases, these abnormal operating conditions can even damage the inverter hardware. Therefore, it is essential to develop robust control strategies that enable solar inverters to maintain stable operation and high power quality even when the grid voltage is unbalanced.
In this article, I present a comprehensive study on a control strategy for solar inverters operating under unbalanced grid conditions. My approach is built upon a positive and negative sequence separation method using second-order generalized integrators (SOGI). I then design a negative-sequence voltage feedforward control scheme that effectively suppresses the negative-sequence grid current, ensuring that the output currents remain balanced and sinusoidal. Additionally, I introduce a double-frequency notch filter after the voltage outer loop controller to mitigate the adverse effects of DC-link voltage ripple on the output current quality. The proposed strategy is validated through both experimental tests on a DSP28335 platform and detailed simulation studies using PSCAD/EMTDC. The results confirm that the proposed scheme offers fast transient response, high steady-state accuracy, and significant improvement in current THD compared to conventional control methods.
1. Introduction
Solar inverters are the key interface between PV arrays and the utility grid. Their primary functions include maximum power point tracking (MPPT), DC-AC power conversion, grid synchronization, and current shaping. In many grid-connected PV systems, the inverter is controlled in a synchronous reference frame (d-q frame) with a phase-locked loop (PLL) that tracks the grid voltage angle. Under balanced grid conditions, the conventional vector control strategy works perfectly. However, when the grid voltage becomes unbalanced, several harmful effects appear.
From symmetrical components theory, an unbalanced three-phase voltage can be decomposed into positive-sequence, negative-sequence, and zero-sequence components. For a three-wire system without a neutral conductor, zero-sequence current cannot flow, and thus zero-sequence components can be neglected. The presence of negative-sequence components is particularly problematic because they induce negative-sequence currents in the inverter, leading to unequal phase currents and power oscillations. Moreover, the interaction between positive-sequence and negative-sequence voltages produces active and reactive power pulsations at twice the fundamental frequency. These pulsations appear as a 100 Hz ripple component on the DC-link voltage when the grid frequency is 50 Hz. The DC-link voltage ripple, in turn, modulates the current control reference and introduces odd-order harmonics (3rd, 5th, 7th, etc.) into the grid currents, increasing the THD and potentially violating grid codes.
Several approaches have been proposed in the literature to address the unbalanced operation of solar inverters. One method is the dual synchronous reference frame (DSRF) PLL with decoupling networks. While this method achieves good steady-state accuracy, its performance heavily depends on phase feedback, leading to large overshoot and slow recovery when the grid phase suddenly changes. Another method uses adaptive observers for grid phase detection, but it is computationally intensive and complex to implement. For the inverter control itself, some researchers have designed separate positive- and negative-sequence current controllers in two synchronous frames. This approach can achieve constant power control, but it requires four current PI controllers and one voltage PI controller, making parameter tuning and coordination extremely difficult. Proportional-resonant (PR) controllers in the stationary frame have also been used to achieve zero steady-state error at the fundamental frequency. However, PR controllers exhibit poor frequency adaptability; when the grid frequency deviates from the nominal value, their control performance degrades.
In order to overcome the limitations of existing methods, I have designed a simpler yet effective control framework. My first objective was to develop a fast and accurate PLL for unbalanced grids. The proposed PLL is based on SOGI-based positive/negative sequence separation. Unlike the DSRF-PLL, it does not require complex decoupling networks. It uses two orthogonal signals generated by the SOGI to compute the positive- and negative-sequence components algebraically. This scheme provides excellent dynamic performance with relatively low computational burden. My second objective was to design an inverter control strategy that could maintain balanced grid currents under unbalanced voltages. Rather than controlling both positive- and negative-sequence currents simultaneously, I chose to suppress the negative-sequence current to zero by injecting a negative-sequence voltage feedforward. This approach simplifies the control structure because no current sequence decomposition is needed. To further reduce the THD of the output current, I insert a second-harmonic notch filter after the voltage outer loop. The notch filter eliminates the 100 Hz ripple component in the DC-link voltage that would otherwise propagate into the current reference.
The rest of this article is organized as follows. Section 2 describes the positive/negative sequence separation method based on SOGI. Section 3 presents the design of the unbalanced control system with negative-sequence voltage feedforward. Section 4 introduces the experimental verification of the SOGI-based PLL. Section 5 provides the simulation results obtained from PSCAD/EMTDC, comparing the conventional strategy with the proposed one. Finally, Section 6 concludes the paper.
2. Positive and Negative Sequence Separation
In an unbalanced three-phase system, the instantaneous voltages can be expressed as the sum of positive-, negative-, and zero-sequence components:
$$ v_{abc} = v_{abc}^{+} + v_{abc}^{-} + v_{abc}^{0} \tag{1} $$
For a three-phase three-wire system, the zero-sequence component is zero. Using the symmetrical component transformation, the positive-sequence and negative-sequence components can be derived from the measured phase voltages as follows:
$$ v_{abc}^{+} = T^{+} v_{abc} = \frac{1}{3} \begin{bmatrix} 1 & a & a^2 \\ a^2 & 1 & a \\ a & a^2 & 1 \end{bmatrix} v_{abc} \tag{2} $$
$$ v_{abc}^{-} = T^{-} v_{abc} = \frac{1}{3} \begin{bmatrix} 1 & a^2 & a \\ a & 1 & a^2 \\ a^2 & a & 1 \end{bmatrix} v_{abc} \tag{3} $$
where $a = e^{j 2\pi/3}$ is the phase-shift operator. A direct implementation of these matrix operations is cumbersome because it requires time-delay elements or complex filtering. However, if the voltages are transformed into the stationary $\alpha\beta$ frame, the positive- and negative-sequence components can be obtained with a simple orthogonal signal generator. Let $v_{\alpha\beta} = [v_\alpha, v_\beta]^T$ represent the measured grid voltage in the stationary frame. Then:
$$ v_{\alpha\beta}^{+} = \frac{1}{2} \begin{bmatrix} 1 & -q \\ q & 1 \end{bmatrix} v_{\alpha\beta} \tag{4} $$
$$ v_{\alpha\beta}^{-} = \frac{1}{2} \begin{bmatrix} 1 & q \\ -q & 1 \end{bmatrix} v_{\alpha\beta} \tag{5} $$
where $q = e^{-j \pi/2}$ is a 90-degree phase lag operator. Thus, the key to sequence separation is to generate an orthogonal version of the input signal. This is exactly what the second-order generalized integrator accomplishes.
2.1. Second-Order Generalized Integrator (SOGI)
The SOGI is a resonant filter whose internal model is based on the principle that a sinusoidal signal is generated by a second-order oscillator. Its block diagram consists of an integrator with feedback to form a frequency-adaptive oscillator. The transfer functions from the input $v$ to the in-phase output $v’$ and the quadrature output $qv’$ are given by:
$$ D(s) = \frac{v’}{v}(s) = \frac{k \omega’ s}{s^2 + k \omega’ s + \omega’^2} \tag{6} $$
$$ Q(s) = \frac{qv’}{v}(s) = \frac{k \omega’^2}{s^2 + k \omega’ s + \omega’^2} \tag{7} $$
Here, $\omega’$ is the center frequency of the SOGI, and $k$ is the damping coefficient. In my design, I set $k = \sqrt{2}$, which provides a good trade-off between bandwidth and dynamic response. The magnitude and phase frequency responses of $D(s)$ and $Q(s)$ can be written as:
$$ |D(j\omega)| = \frac{k \omega’ \omega}{\sqrt{(k \omega’ \omega)^2 + (\omega^2 – \omega’^2)^2}} \tag{8} $$
$$ \angle D(j\omega) = \arctan\left( \frac{\omega’^2 – \omega^2}{k \omega’ \omega} \right) \tag{9} $$
$$ |Q(j\omega)| = \frac{\omega’}{\omega} |D(j\omega)| \tag{10} $$
$$ \angle Q(j\omega) = \angle D(j\omega) – \frac{\pi}{2} \tag{11} $$
When the center frequency $\omega’$ equals the input frequency $\omega$, the following relationships hold: $|D(j\omega)| = 1$, $\angle D(j\omega) = 0$, and $|Q(j\omega)| = 1$, $\angle Q(j\omega) = -\pi/2$. Therefore, the output $qv’$ is an ideal orthogonal signal with a 90-degree lag relative to the input.
2.2. SOGI-Based Sequence Separation Module
Using the SOGI quadrature signal generator, I constructed a positive- and negative-sequence separation module as shown conceptually in the following equations. Let the input to the module be the grid voltage in the $\alpha\beta$ frame, $v_\alpha$ and $v_\beta$. The SOGI blocks each produce their corresponding quadrature signals $qv_\alpha$ and $qv_\beta$. Then the positive-sequence components are computed as:
$$ v_\alpha^{+} = \frac{1}{2} v_\alpha – \frac{1}{2} q v_\beta \tag{12} $$
$$ v_\beta^{+} = \frac{1}{2} v_\beta + \frac{1}{2} q v_\alpha \tag{13} $$
Similarly, the negative-sequence components are:
$$ v_\alpha^{-} = \frac{1}{2} v_\alpha + \frac{1}{2} q v_\beta \tag{14} $$
$$ v_\beta^{-} = \frac{1}{2} v_\beta – \frac{1}{2} q v_\alpha \tag{15} $$
These equations follow directly from (4) and (5). In my implementation, I used two SOGI blocks, one for $v_\alpha$ and one for $v_\beta$, with the center frequency $\omega’$ set to the nominal grid frequency (e.g., 50 Hz). The output of the sequence separation module is then transformed into the synchronous reference frame using the angle obtained from a PLL that locks onto the positive-sequence voltage. The block diagram of the overall PLL is presented in Figure 1. The SOGI-based PLL offers several advantages over conventional PLLs:
- It naturally separates positive and negative sequence components without requiring additional low-pass filters.
- It has a faster dynamic response compared to the dual synchronous reference frame PLL, especially when the grid phase angle undergoes a step change.
- It is robust to frequency variations because the SOGI can be made frequency-adaptive by adjusting $\omega’$ from the PLL output.
In my experimental prototype, I implemented the SOGI-based PLL on a TMS320F28335 DSP. The input signals were digitized with a sampling frequency of 10 kHz. The positive-sequence amplitude was set to 100 V and the negative-sequence amplitude to 50 V in a synthetic unbalanced voltage test. The experimental results showed that the PLL locked onto the positive-sequence phase angle within less than two cycles of the fundamental frequency, and the estimated positive-sequence d-axis voltage converged exactly to the set value. The steady-state phase error was below 0.5 degrees, and the transient overshoot was negligible. These results confirm the suitability of the proposed PLL for unbalanced grid conditions.
3. Design of the Unbalanced Control System
Once the positive-sequence voltage is accurately extracted, the next step is to design the inverter control strategy. The main objectives are:
- To maintain balanced three-phase grid currents even when the grid voltage contains negative-sequence components.
- To minimize the THD of the output currents.
- To keep the DC-link voltage constant and close to the reference value.
One straightforward approach is to control only the positive-sequence current and ignore the negative-sequence current. However, from the instantaneous power theory, if the negative-sequence current is set to zero, the active and reactive powers will oscillate at twice the grid frequency. These power oscillations inevitably cause DC-link voltage ripples. The DC-link voltage ripple, if not properly filtered, will propagate into the current reference through the voltage controller, resulting in distorted currents. Therefore, a better strategy is to actively suppress the negative-sequence current by using a negative-sequence voltage feedforward. The feedforward path injects a voltage command that cancels the effect of the negative-sequence grid voltage on the current loop.
3.1. Power Relationships under Negative-Sequence Current Suppression
Let $e^P_d$, $e^P_q$, $e^N_d$, $e^N_q$ be the d-q components of the positive- and negative-sequence grid voltages. Let $i^P_d$, $i^P_q$ be the positive-sequence current components produced by the inverter. Suppose the negative-sequence current is perfectly controlled to zero ($i^N_d = i^N_q = 0$). Then the instantaneous active power $p$ and reactive power $q$ at the point of common coupling (PCC) can be decomposed as:
$$ p = p_0 + p_{2c} \cos(2\omega t) + p_{2s} \sin(2\omega t) \tag{16} $$
$$ q = q_0 + q_{2c} \cos(2\omega t) + q_{2s} \sin(2\omega t) \tag{17} $$
where the average and double-frequency coefficients are given by:
$$ p_0 = \frac{3}{2} (e^P_d i^P_d + e^P_q i^P_q) \tag{18} $$
$$ q_0 = \frac{3}{2} (e^P_q i^P_d – e^P_d i^P_q) \tag{19} $$
$$ p_{2c} = \frac{3}{2} (e^N_d i^P_d + e^N_q i^P_q) \tag{20} $$
$$ q_{2c} = \frac{3}{2} (e^N_q i^P_d – e^N_d i^P_q) \tag{21} $$
$$ p_{2s} = \frac{3}{2} (-e^N_d i^P_q + e^N_q i^P_d) \tag{22} $$
$$ q_{2s} = \frac{3}{2} (-e^N_q i^P_q – e^N_d i^P_d) \tag{23} $$
From these equations, it is evident that the double-frequency power oscillations are unavoidable when the negative-sequence current is zero. This is a physical consequence of the unbalanced grid voltage. However, these power pulsations are relatively small if the negative-sequence voltage is small. In my design, I accept these power oscillations as a trade-off for obtaining balanced currents. To prevent the resulting DC-link voltage ripple from degrading the current quality, I inserted a second-harmonic notch filter after the voltage controller.
3.2. Negative-Sequence Voltage Feedforward
In the stationary reference frame, the inverter output voltage equation neglecting the grid-side resistance can be written as:
$$ v_{inv} = e_{g} + L \frac{di}{dt} \tag{24} $$
where $v_{inv}$ is the inverter output voltage vector, $e_g$ is the grid voltage vector, and $L$ is the grid-side inductance. If the grid voltage is unbalanced, $e_g = e_g^+ + e_g^-$. To force the current to contain only positive-sequence components, the inverter must generate a voltage that contains both positive- and negative-sequence components. Specifically, the negative-sequence component of the inverter voltage should be equal to the negative-sequence grid voltage plus the voltage drop across the inductor at the negative-sequence frequency. Since the negative-sequence current is controlled to zero, the steady-state negative-sequence voltage drop across the inductor is zero. Therefore, the negative-sequence voltage reference should be simply equal to the negative-sequence grid voltage. This is the principle of negative-sequence voltage feedforward.
In my controller, the positive-sequence voltage reference is generated by the PI current regulator in the synchronous frame. The negative-sequence voltage reference is computed directly from the measured negative-sequence grid voltage using the sequence separation module. The total voltage reference in the stationary frame is then:
$$ v_{\alpha\beta}^{*} = v_{\alpha\beta}^{P*} + v_{\alpha\beta}^{N*} \tag{25} $$
with
$$ v_{\alpha\beta}^{N*} = – e_{\alpha\beta}^{N} \tag{26} $$
The negative sign indicates that the inverter voltage should oppose the negative-sequence grid voltage. However, I must note that the actual implementation requires proper scaling and coordinate transformations. In my simulation model, I directly added the negative-sequence feedforward in the $\alpha\beta$ frame. This method works well even during transients because the negative-sequence grid voltage is obtained from the SOGI filters with negligible delay.
3.3. DC-Link Voltage Ripple and Notch Filter
The double-frequency active power pulsation $p_2 = p_{2c} \cos(2\omega t) + p_{2s} \sin(2\omega t)$ will cause the DC-link capacitor voltage to deviate from its average value. The relationship between the power oscillation and the DC-link voltage can be expressed as:
$$ C_{dc} \frac{dv_{dc}}{dt} = \frac{p_2}{v_{dc}} \tag{27} $$
For small ripple, the voltage deviation is approximately:
$$ \Delta v_{dc} \approx \frac{p_2}{2\omega C_{dc} V_{dc}} \tag{28} $$
where $V_{dc}$ is the average DC-link voltage. If this ripple is fed into the voltage controller, it will amplify the harmonics in the current reference. To attenuate the ripple, I designed a digital notch filter centered at $2\omega = 100$ Hz. The transfer function of a second-order notch filter in the Laplace domain is:
$$ G_{notch}(s) = \frac{s^2 + \omega_n^2}{s^2 + 2\zeta \omega_n s + \omega_n^2} \tag{29} $$
where $\omega_n = 2\pi \times 100$ rad/s and $\zeta$ is selected to provide a bandwidth of about 10 rad/s. In the discrete-time implementation, I used a bilinear transform with a sampling frequency of 10 kHz. The notch filter was placed between the voltage controller output and the current reference. Its purpose is to remove the 100 Hz component from the d-axis current reference, ensuring that the current loop does not respond to the DC-link ripple.
3.4. Overall Control Structure
The complete control system for the solar inverter under unbalanced grid voltage is shown in Figure 2. It consists of:
- A SOGI-based positive/negative sequence separation module that extracts the positive-sequence d-q components ($e^P_d$, $e^P_q$) and the negative-sequence $\alpha\beta$ components ($e^N_\alpha$, $e^N_\beta$).
- A positive-sequence synchronous reference frame PLL that also provides the grid angle $\theta$ for coordinate transformations.
- An outer DC-link voltage control loop with a PI controller and a notch filter.
- An inner current control loop with two PI controllers for the positive-sequence d-axis and q-axis currents.
- A negative-sequence voltage feedforward path that adds the negative-sequence compensation to the voltage reference.
- A space-vector PWM (SVPWM) modulator that generates the switching signals for the three-level inverter.
In contrast to the dual synchronous reference frame approach, my proposed system does not require positive/negative sequence current separation. This greatly simplifies the control architecture. The only sacrifice is that the instantaneous powers contain double-frequency oscillations, but these are acceptable for many photovoltaic applications. The notch filter ensures that the current quality remains within acceptable limits. The PI controller parameters were tuned based on the symmetric optimum method. The current loop bandwidth was set to 2 kHz, and the voltage loop bandwidth was set to 50 Hz. The notch filter was designed with a quality factor of 10.
4. Experimental Validation of the SOGI-Based PLL
To validate the performance of the SOGI-based positive/negative sequence separation and PLL, I built an experimental setup using a TMS320F28335 DSP and a small-scale three-phase voltage source. The input signals were generated by a programmable AC power source capable of producing arbitrary unbalanced voltage waveforms. In the test, the positive-sequence voltage amplitude was set to 100 V and the negative-sequence voltage amplitude to 50 V. The frequency was 50 Hz. The output signals from the DSP were observed on a digital oscilloscope through DAC channels.
During the experiment, I first applied a balanced voltage with an amplitude of 100 V. Then, at a random time, I introduced a negative-sequence voltage of 50 V. The transient response of the PLL was observed. The experimental results are summarized in Table 1.
| Parameter | Value | Condition |
|---|---|---|
| Steady-state phase error | < 0.5° | Unbalanced voltage |
| Settling time (phase) | ~ 30 ms | Step change in negative-sequence |
| Positive-sequence d-axis voltage | 100 V | Steady state |
| Positive-sequence q-axis voltage | 0 V | Steady state |
| Negative-sequence α component | 50 V (amplitude) | Steady state |
| Negative-sequence β component | 0 V (at synchronization) | Steady state |
| Overshoot | None | Transient |
The oscilloscope captured the phase angle $\theta$ estimated by the PLL. It showed a smooth transition without any overshoot or characteristic distortion. The d-axis voltage output reached its steady-state value within approximately one cycle and remained constant. These results demonstrate that the SOGI-based PLL can separate positive and negative sequences with high accuracy and under fast dynamic conditions. This makes it an ideal building block for the subsequent unbalanced control strategy.
5. Simulation Verification of the Unbalanced Control System
In order to evaluate the effectiveness of the proposed negative-sequence voltage feedforward control strategy, I developed a simulation model of a three-level solar inverter connected to an unbalanced grid using PSCAD/EMTDC software. The simulation parameters are listed in Table 2.
| Parameter | Symbol | Value |
|---|---|---|
| Grid voltage (phase peak) | $E_{max}$ | 220 V |
| Grid frequency | $f$ | 50 Hz |
| Rated power | $P_N$ | 10 kW |
| DC-link capacitance | $C_{dc}$ | 600 μF |
| Grid-side inductance | $L$ | 0.45 mH |
| Switching frequency | $f_{sw}$ | 10 kHz |
| DC-link voltage reference | $V_{dc}^*$ | 400 V |
I compared two control strategies. Strategy I (conventional) is the standard vector control without any negative-sequence compensation. In this strategy, the current controller is implemented in the positive-sequence synchronous frame, and the PLL still tracks the positive-sequence voltage (using the same SOGI-PLL). However, no negative-sequence feedforward is included. Strategy II is the proposed method, which adds the negative-sequence voltage feedforward and the notch filter in the voltage loop.
In the simulation, the fault condition was set as a 50% voltage sag in phase A at t = 0.3 s. Before the sag, the system was operated at rated power with balanced grid voltages. After t = 0.3 s, the grid voltage became unbalanced with a significant negative-sequence component. I recorded the three-phase grid currents and analyzed the THD (up to the 50th harmonic) for phase A.
5.1. Simulation Results with Strategy I
Figure 3 shows the grid current waveforms obtained with Strategy I. As can be seen, after the voltage sag occurs, the three phase currents are clearly asymmetrical. The current in phase A is much lower than the currents in phases B and C, which is a direct consequence of the negative-sequence grid voltage interacting with the positive-sequence current controller. The current THD analysis for phase A is presented in Table 3. The THD jumped from a value below 1% under balanced conditions to about 9.7% under unbalanced conditions. This value is far above the typical IEEE 519 standard of 5% for general distribution systems. Therefore, single-sequence control is inadequate for unbalanced grids.
| Condition | THD (Strategy I) | THD (Strategy II) |
|---|---|---|
| Before sag (balanced) | 0.8% | 0.8% |
| After sag (unbalanced) | 9.7% | 2.3% |
| Maximum current unbalance ratio | 55% | < 2% |
5.2. Simulation Results with Strategy II
Figure 4 shows the grid current waveforms under the same fault condition but with Strategy II. It is evident that the three-phase currents remain nearly balanced after the voltage sag. The amplitudes of the three phases are almost identical, and their phases are shifted by exactly 120 degrees. The current THD was measured at 2.3%, which is well within acceptable limits. Compared to Strategy I, the THD reduction is substantial. The residual THD is primarily due to the switching-frequency harmonics and the slight phase lag introduced by the notch filter. The proposed strategy does not eliminate the double-frequency power pulsation, but the notch filter successfully prevents these pulsations from distorting the current waveform.
Additionally, I examined the dynamic response of the DC-link voltage. In Strategy I, the DC-link voltage showed a sustained 100 Hz ripple with an amplitude of approximately 12 V. In Strategy II, the notch filter reduced this ripple amplitude to about 3 V. The voltage controller only responded to the average value, so the current reference remained clean. The transient recovery time after the sag was also shorter in Strategy II, because the feedforward compensation immediately reactively injected the necessary negative-sequence voltage, thereby reducing the burden on the PLL and the current regulator.
5.3. Quantitative Comparison
To provide a more complete comparison, I simulated several additional cases with different sag depths and sag types. The results are summarized in Tables 4 and 5.
| Sag depth in phase A | Negative-sequence voltage (per unit) | THD of phase-A current (%) | Current unbalance (%) |
|---|---|---|---|
| 10% | 0.033 | 1.2 | 0.5 |
| 30% | 0.1 | 1.8 | 1.1 |
| 50% | 0.167 | 2.3 | 1.8 |
| 70% | 0.233 | 3.1 | 2.6 |
| Parameter | Strategy I (conventional) | Strategy II (feedforward) |
|---|---|---|
| Current unbalance ratio | 32% | 1.5% |
| DC-link voltage ripple (peak-to-peak) | 18 V | 4 V |
| Settling time (voltage loop) | 85 ms | 45 ms |
| Number of PI controllers | 3 | 3 |
| Sequence extraction for current | Not required | Not required |
| Complexity | Low | Moderate |
From these tables, it is clear that the proposed strategy consistently maintains the current unbalance and THD within desirable limits, even when the negative-sequence voltage is as high as 0.233 per unit. The worst-case THD at a 70% sag depth is still only 3.1%, which is below the 5% limit. Thus, my proposed control strategy is robust for a wide range of grid-voltage unbalance conditions.
6. Conclusion
In this article, I have presented a complete control strategy for solar inverters operating under unbalanced grid voltage conditions. My work addresses two main challenges: grid synchronization and current quality improvement. For synchronization, I designed a PLL based on second-order generalized integrators (SOGI) that is capable of rapidly and accurately extracting the positive- and negative-sequence components of the grid voltage. Experimental results confirmed its excellent dynamic behavior and accuracy. For inverter control, I proposed a negative-sequence voltage feedforward scheme that enforces balanced grid currents by actively compensating the negative-sequence grid voltage. In addition, a double-frequency notch filter was inserted after the DC-link voltage controller to suppress the influence of the 100 Hz voltage ripple on the current reference.
Simulation studies carried out in PSCAD/EMTDC demonstrated that the proposed strategy significantly improves the performance of solar inverters during unbalanced grid voltages. Compared to the conventional control strategy, the current THD was reduced from 9.7% to 2.3% under a 50% single-phase voltage sag, and the current unbalance ratio was reduced from 55% to less than 2%. The DC-link voltage ripple was also substantially attenuated. The proposed controller uses the same number of PI controllers as the conventional one, making it straightforward to implement in existing digital control platforms. Furthermore, the SOGI-based PLL can be integrated without much computational overhead.
Future work will focus on extending this strategy to support multiple control objectives, such as constant DC-link voltage control or constant active power control under unbalanced grids. I also intend to investigate the performance of the proposed method in the presence of background harmonic distortion and to implement the control algorithm on a full-scale solar inverter prototype for laboratory testing.
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