In the rapidly evolving landscape of renewable energy, the inverter serves as the critical bridge between power generation sources and the electrical grid. My research focuses on a particular class of power electronic interfaces, specifically addressing the challenges faced by grid-connected systems. The increasing penetration of renewable energy sources necessitates a deep understanding of the various types of solar inverters, as their performance dictates the stability and quality of power delivered. Among the many types of solar inverters, the three-phase voltage-type PWM inverter is a dominant topology, especially in utility-scale applications. The primary challenge in integrating these types of solar inverters lies in achieving robust synchronization with the grid under various disturbances. Traditional phase-locked loops (PLLs), while fundamental, often exhibit slow dynamic response and poor accuracy, leading to voltage frequency offsets and phase errors. To address these limitations, I have developed a novel double-loop inertia phase-locked loop (DPLL) based on a voltage-current double closed-loop control structure, specifically designed for grid-connected inverters.
This image illustrates a modern residential solar inverter, a crucial component among the various types of solar inverters. My work aims to improve the control algorithms within such devices to enhance their grid interaction. The core of my proposed system involves a meticulous analysis of the main circuit and control architecture of a three-phase PWM inverter using Clarke and Park coordinate transformation theory. This theoretical foundation allows me to derive a sophisticated control strategy that significantly outperforms conventional methods, particularly in scenarios with grid disturbances. The novel DPLL I propose integrates a frequency-locked loop (FLL) and a phase-locked loop (PLL), working in concert to provide superior grid synchronization. This dual-loop structure, combined with inertial control of the phase angle, provides robust anti-interference capabilities, effectively minimizing frequency deviations and phase errors that plague traditional systems.
2. Main Circuit of the Three-Phase Voltage-Type PWM Inverter
The main circuit of the three-phase voltage-type PWM inverter is the power stage responsible for converting direct current (DC) to alternating current (AC). The core components include six identical IGBTs (Q1-Q6), which are switched at high frequency to shape the output voltage. On the AC side, a parallel capacitor C and a series resistor R and inductor L form a filter to attenuate the high-frequency switching harmonics, yielding a clean sinusoidal voltage. The electrical model in the three-phase stationary coordinate system is complex due to coupling between phases. To simplify control, I apply the Park transformation to convert the model into a two-phase rotating coordinate system (dq-frame). In this frame, the state variables are the d-axis and q-axis currents (i_d, i_q) and voltages (U_d, U_q). The dynamic relationship between these quantities is fundamental and is described by the following equation:
$$
\begin{aligned}
L \frac{di_d}{dt} &= U_d – R i_d + \omega L i_q \\
L \frac{di_q}{dt} &= U_q – R i_q – \omega L i_d
\end{aligned}
$$
Here, ω represents the grid’s angular frequency. This equation describes the dynamic voltage and current relationship in the synchronous rotating frame. By controlling U_d and U_q, I can independently control the active and reactive power flow, which is a key advantage for decoupled control strategies in many types of solar inverters.
3. Control Strategy for the Three-Phase Voltage-Type PWM Inverter
3.1 System Control Structure
The control architecture I employ is a dual closed-loop system consisting of an outer voltage loop and an inner current loop. The voltage loop regulates the output voltage amplitude, while the current loop ensures fast and accurate current tracking. The reference voltages U_d^* and U_q^* are generated based on the control objectives. The control block diagram is centered around these two loops. The active power P, after passing through a low-pass filter, is compared with a reference signal. The error is processed by a PI controller to generate the d-axis reference current i_d^*. Similarly, the voltage amplitude U_o is filtered and compared with its reference to generate the q-axis reference current i_q^*. A switching mechanism introduces a correction signal δ after a pre-defined time (t ≥ 1s) to enhance dynamic performance. These currents are then processed by inner-loop PI controllers, with feed-forward compensation terms (K i_d, K i_q, U_d, U_q) being added to improve decoupling and transient response. The resulting voltage references U_d^* and U_q^* are transformed back to the three-phase stationary frame using the phase angle θ provided by the DPLL, thus generating the PWM gating signals for the IGBTs.
3.2 Controller Parameter Design
The design of the PI controller parameters is critical for stability and performance. The process begins by defining the system’s operating point. Assuming the DC-link voltage is U, the voltage equations in the dq-frame can be rearranged. The d-axis current controller is designed to track i_d^*. The control law for the d-axis PI controller is:
$$
U_d^* = (K_{p\_id} + \frac{K_{i\_id}}{s})(i_d^{ref} – i_d) – \omega L i_q + U_d
$$
In this equation, K_{p\_id} and K_{i\_id} are the proportional and integral gains for the d-axis current controller. The terms -ωL i_q and U_d are feed-forward compensation terms. The system’s open-loop transfer function for the d-axis current loop is:
$$
G_{ol\_id}(s) = (K_{p\_id} + \frac{K_{i\_id}}{s}) \cdot \frac{1}{R + sL}
$$
The closed-loop transfer function is then:
$$
G_{cl\_id}(s) = \frac{G_{ol\_id}(s)}{1 + G_{ol\_id}(s)} = \frac{K_{p\_id}s + K_{i\_id}}{L s^2 + (R + K_{p\_id})s + K_{i\_id}}
$$
I use pole placement to select K_{p\_id} and K_{i\_id}. For a desired damping ratio ζ and natural frequency ω_n, the gains are calculated. Generally, K_{p\_id} is related to L and the desired bandwidth, while K_{i\_id} is chosen to eliminate steady-state error. Similarly, the q-axis current controller gains (K_{p\_iq}, K_{i\_iq}) are designed using the same methodology, with its open-loop transfer function being identical in form.
The outer voltage loop is inherently slower. Its PI controller gains for the d and q axes (K_{p\_ud}, K_{i\_ud} and K_{p\_uq}, K_{i\_uq}) are designed with a lower bandwidth to ensure stability and to filter out higher-frequency current ripple. The selection of these parameters directly influences how effectively the inverter can manage various operating conditions, a crucial aspect for all types of solar inverters.
The following table summarizes the finalized PI controller parameters after simulation-based optimization:
| Control Loop | Axis | Proportional Gain (K_p) | Integral Gain (K_i) |
|---|---|---|---|
| Current Loop (Inner) | d-axis | 0.468 | 9.36 |
| q-axis | 0.535 | 10.7 | |
| Voltage Loop (Outer) | d-axis | 5 | 16 |
| q-axis | 5 | 16 |
4. Structure and Control Principle of the Double-Loop Inertia PLL (DPLL)
4.1 Structure of the DPLL
The proposed DPLL is designed to overcome the limitations of standard PLLs, especially in weak grid conditions. Its structure is distinct, featuring a frequency-locked loop (FLL) and a phase-locked loop (PLL) working in tandem. The input to the DPLL is the three-phase voltage U_abc, which is transformed into the dq-frame voltages U_d and U_q using Clarke and Park transformations. The core innovation lies in the dual feedback loops. The FLL uses the q-axis voltage U_q as an error indicator. This error is processed by a PID controller to output an estimated frequency deviation, ω̂. This estimate is then compared with the nominal grid frequency (2π*50 rad/s) to generate a frequency error signal, ω_error. This error is integrated to yield the actual grid frequency ω, which is fed back to the FLL input. This process forces the FLL’s output frequency to accurately track the grid frequency. The phase-locked loop (PLL) then takes over. It sums the frequency deviation ω error and the estimated frequency ω̂ to get the instantaneous angular frequency ω(t). This is integrated to produce the estimated phase angle θ(t). The phase angle is fed back and compared with the actual phase, and the resulting error is integrated to yield a phase difference δ. A controller adjusts the output to achieve phase lock.
4.2 Control Principle of the DPLL
The control principle can be described by transfer functions. The FLL’s transfer function, G_f(s), can be represented as:
$$
G_f(s) = \frac{\omega(s)}{U_q(s)}
$$
Where the FLL uses the PID controller to minimize the frequency error. The PLL’s transfer function, G_p(s), integrates the frequency to obtain the phase:
$$
G_p(s) = \frac{1}{s}
$$
The overall transfer function G(s) for the DPLL, from U_abc to the output phase θ, is a combination of these two loops. The PID controller gains within the FLL are the most critical parameters for stability. A careful balance is required to ensure fast response without introducing oscillations. The stability of the dual-loop structure is ensured by designing the FLL (inner loop) to have a higher bandwidth than the PLL (outer loop). This separation of time scales prevents the two loops from interfering with each other. The convergence of the DPLL depends on the gains of the PID controller. The proportional gain (Kp) primarily determines the speed of convergence, while the integral gain (Ki) is crucial for eliminating steady-state errors. The derivative gain (Kd) helps to dampen overshoot and improve transient response. The relationship between these gains and the system’s damping ratio ζ is key to achieving robust performance.
5. Simulation Results and Analysis
To validate the performance of the proposed DPLL, I built a simulation model using Matlab/Simulink for the three-phase voltage-type PWM inverter. The simulation parameters are listed in the table below.
| Parameter | Symbol | Value |
|---|---|---|
| DC Input Voltage | U | 600 V |
| AC Side Resistance | R | 6.4 mΩ |
| AC Side Inductance | L | 2 mH |
| Filter Capacitance | C | 1 μF |
| Grid Frequency (nominal) | f | 50 Hz |
The simulation was run for 5 seconds. I first tested the system with a conventional PLL to establish a baseline for comparison. The output waveforms for voltage frequency and phase difference (δ) are described. For the conventional PLL, the voltage frequency showed significant fluctuations. After approximately 1.0 second, the frequency dipped to about 49.9 Hz before oscillating around 50 Hz. At times t = 1.5, 2.0, 2.5, and 3.0 seconds, the frequency signal exhibited sharp spikes, deviating upward before slowly decaying back toward 49.95 Hz. This behavior indicates that the conventional PLL struggles to maintain a steady lock, especially under minor disturbances or transients within the system. The phase difference (δ) signal also showed poor performance. After an initial settling period of about 0.5 seconds, the phase error approached zero. However, at the same time instants (t = 1.5 to 3.0 seconds) where the frequency spiked, the phase error also exhibited large, oscillatory spikes. The entire waveform continued to oscillate, demonstrating the conventional PLL’s susceptibility to noise and its limited phase tracking accuracy.
I then replaced the conventional PLL with my proposed double-loop inertia PLL (DPLL). The results were markedly different and significantly better. The voltage frequency output from the inverter stabilized very quickly. After a brief initial transient of about 0.5 seconds, the frequency locked onto the nominal 50 Hz and remained perfectly stable for the remainder of the simulation, with no observable fluctuations or spikes. Similarly, the phase difference (δ) signal showed excellent performance. After the same initial transient period (t = 0.5s), the phase error remained at a stable value of zero with only negligible, low-amplitude oscillations. The DPLL demonstrated superior disturbance rejection and accurate tracking of the grid’s frequency and phase. This performance is a direct result of the dual-loop structure and the inertial control acting on the phase angle, which effectively filters out high-frequency disturbances and provides a clean, stable synchronized signal.
6. Conclusion
Through rigorous theoretical analysis and simulation, I have demonstrated that the proposed double-loop inertia phase-locked loop (DPLL) significantly outperforms conventional PLLs when integrated with a three-phase voltage-type PWM inverter. The DPLL is particularly effective in mitigating the adverse effects of grid disturbances, such as voltage frequency shifts and phase errors. Its dual-loop control structure, combining a frequency-locked loop and a phase-locked loop, provides a robust mechanism for accurate grid synchronization. The inertial control of the phase angle enhances the system’s anti-interference capability, leading to a dramatic reduction in frequency and phase deviations compared to the conventional PLL. The simulation results validate that the DPLL can lock onto the grid frequency and phase more quickly and maintain a more stable lock under test conditions, ensuring a higher quality of power injection from the inverter. This enhanced synchronization capability is a key requirement for the safe and stable integration of all types of solar inverters into modern power grids. The DPLL presents a highly effective and practical solution for improving the resilience of grid-connected inverters, paving the way for a more stable and reliable renewable energy infrastructure. The DPLL-based control strategy is a valuable contribution to the field of power electronics and grid integration, offering a superior alternative for high-performance inverter systems.