In the field of photovoltaic systems, the selection of appropriate types of solar inverters is crucial for system efficiency, power quality, and safety. Traditional types of solar inverters often face challenges such as complex structures and the necessity to eliminate leakage currents. To address these issues, we propose a novel neutral-point clamped (NPC) five-level grounded inverter. This proposed inverter integrates a front-end NPC three-level circuit with a rear-end common-ground switched capacitor structure, all connected through a single filter inductor. The topology consists of one DC input source, six power switches, three diodes, and three capacitors. It is designed to output five distinct voltage levels, which significantly improves the output waveform quality. Furthermore, the inherent ground connection in the topology effectively eliminates leakage currents, thereby reducing electromagnetic interference (EMI) and power losses while enhancing the overall safety and stability of the system. Our work involves a comprehensive analysis of the inverter’s topology, operational principles, and self-voltage balancing capability. We also present a carrier-based level-shifted pulse-width modulation (PWM) strategy and the parameter design methodology for the output filter inductor. The theoretical findings are validated through simulations conducted in a MATLAB/Simulink environment.
Introduction and Motivation
The pursuit of high power quality and high power density has made multilevel inverters a cornerstone in distributed photovoltaic applications. While traditional topologies like the neutral-point clamped (NPC), flying capacitor, T-type, and cascaded H-bridge are technically mature, each possesses inherent drawbacks. For instance, the NPC inverter is notorious for its DC-link neutral-point potential imbalance. The flying capacitor inverter introduces high capacitor stress, increasing costs. The T-type inverter exposes certain switches to high voltage stress. Lastly, the cascaded H-bridge inverter requires an excessive number of components, which adds to its cost and complexity.
To overcome these limitations, researchers have proposed various improved topologies. Some have optimized the cascaded H-bridge to increase voltage levels while reducing voltage stress on switches, but their total harmonic distortion (THD) can remain high. Others have integrated switched-capacitor circuits with full-bridge structures to achieve nine levels with fewer components and lower stress, but their power rating can be constrained by the switched-capacitor design. Building upon these insights, our proposed five-level grounded inverter offers a unique solution. It operates without a traditional H-bridge to achieve multilevel inversion, ensures low voltage stress on all switches, simplifies the modulation scheme, and effectively eliminates common-mode currents by creating a direct ground path for the system. This makes it particularly well-suited for grid-tied or off-grid solar applications where safety and efficiency are paramount. This work analyzes the topology, its operational principles, the self-voltage balancing of its capacitor, and a suitable modulation strategy, culminating in simulation-based validation.
Topology and Operational Principle Analysis
Inverter Topology
The proposed NPC five-level grounded inverter, as shown in the conceptual diagram, comprises a front-end NPC three-level circuit that inverts the DC voltage into a three-level AC waveform and a rear-end common-ground switched capacitor stage that adds an extra PWM level and filtering. The specific components include six power MOSFETs (S1 to S6), where S5 and S6 operate in a complementary manner; three diodes (D1, D2, D3); three capacitors (C1, C2, C3); and one filter inductor (L1). A key feature is the direct connection of the NPC circuit’s neutral point to the common ground of the rear-end structure. This arrangement not only helps mitigate the neutral-point imbalance issue common in NPC circuits but also allows for a more compact filter design by improving the output waveform quality. The ground connection is the primary mechanism for eliminating common-mode leakage currents, a critical requirement for many photovoltaic systems.
Operating States and Mode Analysis
To simplify our analysis, we assume all switches and voltage sources are ideal and that the capacitors are sufficiently large to maintain constant voltages and provide steady output current. The switches S5 and S6 operate complementarily, while S1 and S4 are never turned on simultaneously. The inverter has eight distinct switching states that generate five different voltage levels (+Vin, +Vin/2, 0, -Vin/2, -Vin).
State (a): +Vin Level
Switches S1, S2, and S5 are ON. Switches S3, S4, and S6 are OFF. Diodes D1 and D2 are reverse-biased, while D3 is forward-biased. Capacitor C3 is being charged from the source. The output voltage is +Vin.
State (b): +Vin/2 Level
Switches S2 and S5 are ON. Switches S1, S3, S4, and S6 are OFF. Diode D1 is forward-biased, while D2 and D3 are reverse-biased. The output voltage is +Vin/2.
State (c): +Vin/2 Level
Switches S3 and S5 are ON. Switches S1, S2, S4, and S6 are OFF. Diode D2 is forward-biased, while D1 and D3 are reverse-biased. The output voltage is +Vin/2.
State (d): 0 Level
Switches S3, S4, and S5 are ON. Switches S1, S2, and S6 are OFF. Diodes D1, D2, and D3 are all reverse-biased. The output voltage is 0.
State (e): 0 Level
Switches S1, S2, and S6 are ON. Switches S3, S4, and S5 are OFF. Diodes D1 and D2 are reverse-biased, while D3 is forward-biased. Capacitor C3 is charged. The output voltage is 0.
State (f): -Vin/2 Level
Switches S2 and S6 are ON. Switches S1, S3, S4, and S5 are OFF. Diode D1 is forward-biased, while D2 and D3 are reverse-biased. Capacitor C3 is charged. The output voltage is -Vin/2.
State (g): -Vin/2 Level
Switches S3 and S6 are ON. Switches S1, S2, S4, and S5 are OFF. Diodes D1 and D2 are reverse-biased, while D3 is forward-biased. Capacitor C3 is discharging. The output voltage is -Vin/2.
State (h): -Vin Level
Switches S3, S4, and S6 are ON. Switches S1, S2, and S5 are OFF. Diodes D1, D2, and D3 are all reverse-biased. Capacitor C3 is discharging. The output voltage is -Vin.
For clarity, the switch states, capacitor action, and resulting output voltage for each of the eight modes are summarized in the table below, where “1” indicates an ON state and “0” indicates an OFF state for the switches. For the capacitor C3, “C” denotes charging, “D” denotes discharging, and “-” denotes an idle state.
| Mode | S1 | S2 | S3 | S4 | S5 | S6 | C3 State | Vo |
|---|---|---|---|---|---|---|---|---|
| (a) | 1 | 1 | 0 | 0 | 1 | 0 | C | Vin |
| (b) | 0 | 1 | 0 | 0 | 1 | 0 | – | Vin/2 |
| (c) | 0 | 0 | 1 | 0 | 1 | 0 | – | Vin/2 |
| (d) | 0 | 0 | 1 | 1 | 1 | 0 | – | 0 |
| (e) | 1 | 1 | 0 | 0 | 0 | 1 | C | 0 |
| (f) | 0 | 1 | 0 | 0 | 0 | 1 | C | -Vin/2 |
| (g) | 0 | 0 | 1 | 0 | 0 | 1 | D | -Vin/2 |
| (h) | 0 | 0 | 1 | 1 | 0 | 1 | D | -Vin |
Capacitor Self-Voltage Balancing
An important self-balancing property is exhibited by capacitor C3. As shown in the operational table, C3 is charged when it is connected in parallel with the input source during states (a) and (e). Conversely, it is discharged when it provides the load current during states (g) and (h). In the negative half-cycle, the net charge supplied to the capacitor during the charging states is balanced by the net charge withdrawn during the discharging states. Over one complete cycle of the AC output voltage, the voltage across capacitor C3 remains dynamically balanced at a value equal to the input voltage Vin. This inherent self-balancing mechanism eliminates the need for complex external control loops dedicated to voltage regulation of C3, significantly simplifying the control system and enhancing reliability.
Modulation Strategy and Filter Design
Carrier-Based Level-Shifted PWM (LS-PWM)
The inverter is controlled using a carrier-based level-shifted PWM (LS-PWM) strategy. This technique is well-regarded for its ability to suppress voltage harmonics and is straightforward to implement in multilevel inverters. For a five-level output, four triangular carrier signals of the same frequency and amplitude are arranged in a vertical (level-shifted) fashion. A single sinusoidal modulating wave is compared with these carriers. The output voltage level is determined by which carrier the modulating wave is compared against. Specifically:
- When the modulating wave is above the positive-most carrier, the output is +Vin.
- When it is between the two positive carriers, the output is +Vin/2.
- When it is between the positive and negative carriers, the output is 0.
- When it is between the two negative carriers, the output is -Vin/2.
- When it is below the negative-most carrier, the output is -Vin.
The relationship between the modulation index \( M \) and the output voltage is critical. The modulation index \( M \) is defined as the ratio of the amplitude of the modulating wave \( A_r \) to the peak-to-peak amplitude of the carrier waves (which is \( 2A_c \) for four carriers). The formula is:
$$ M = \frac{A_r}{2A_c} $$
The number of output levels is directly dependent on the modulation index \( M \). When \( M \) is greater than 0.5, the modulating wave is high enough to intersect all carrier levels, allowing the inverter to output all five voltage levels. However, when \( M \) is less than 0.5, the modulating wave only intersects the inner carriers, resulting in a three-level output and effectively halving the voltage gain. This relationship is crucial for understanding the inverter’s operating range and output voltage controllability.
Filter Inductor Design
The design of the output filter inductor is a trade-off between minimizing voltage drop, limiting current ripple, and managing component size and cost. Two primary constraints govern the design of the inductor L1.
1. Voltage Drop Constraint:
The voltage drop across the inductor must be limited to a small fraction of the output voltage to ensure good voltage regulation. We impose a constraint that the voltage drop at the fundamental frequency (f) should be less than 5% of the nominal output voltage (U). The equation for the inductor voltage drop is:
$$ L \frac{di}{dt} \leq 5\% U $$
This can be reformulated to give an upper limit for the inductance:
$$ L \leq \frac{5\% U}{2\pi f I} $$
where \( I \) is the load current. This constraint ensures that the filter does not cause a significant voltage drop under rated load conditions.
2. Current Ripple Constraint:
Conversely, to prevent excessive current ripple that can increase switching losses and complicate control, a lower limit for the inductance is established. We set the maximum allowable current ripple \( \Delta I_{max} \) to be less than 20% of the peak rated current \( I_{max} \):
$$ \Delta I_{max} \leq 20\% I_{max} $$
The maximum current ripple for a typical inductor in a PWM converter can be approximated as:
$$ \Delta I_{max} = \frac{V}{4 L f_n} $$
where \( V \) is the voltage applied across the inductor and \( f_n \) is the switching frequency. By combining these two equations, we can derive a lower bound for the inductance to meet the ripple requirement:
$$ L \geq \frac{V}{4 I_{max} f_n} $$
The final chosen value for the filter inductor must satisfy both the upper limit from the voltage drop constraint and the lower limit from the current ripple constraint. This ensures that the filter performs effectively without degrading the output voltage quality or system efficiency.
Simulation Results and Validation
To validate the theoretical analysis and the effectiveness of the proposed topology, a model of the five-level grounded inverter was built and simulated using MATLAB/Simulink. The key simulation parameters used are listed in the table below.
| Parameter | Value |
|---|---|
| Filter Inductance (L1) | 2 mH |
| Filter Capacitance | – |
| Capacitors C1, C2 | 0.5 mF |
| Floating Capacitor C3 | 2 mF |
| Input Voltage (Vin) | 400 V |
| Modulation Index (M) | 0.9 |
| Switching Frequency (fn) | 10 kHz |
Simulation with M = 0.9
When operating with a modulation index of 0.9, the inverter successfully generated the expected five-level output voltage waveform. The filtered output was a smooth, high-quality AC sine wave with low distortion. A spectral analysis conducted after the initial transient period (starting from 0.5 s) showed that the total harmonic distortion (THD) of the output voltage was only 0.87%. This extremely low THD value confirms the inverter’s ability to produce a high-quality output waveform, which is a significant advantage for sensitive loads and grid connections. The performance of the LS-PWM modulation scheme was also verified in simulation, showing the correct generation of the gate pulses for the six switches.
Simulation with M = 0.45
To test the inverter’s behavior at a lower modulation index, a simulation was performed with M = 0.45. As predicted by the theory, the inverter output a three-level waveform instead of a five-level one because the modulating wave did not reach the outermost carrier levels. Despite the reduction in voltage levels, the output quality remained high. The spectral analysis for this case, also starting from 0.5 s, revealed a THD of 0.86%. This demonstrates the inverter’s robust performance and ability to maintain a low THD across different operating conditions, which is a desirable trait for various types of solar inverters.
Conclusion
In this work, we have presented a novel neutral-point clamped five-level grounded inverter. Our analysis and simulation results confirm that this topology offers several distinct advantages over traditional types of solar inverters. First, it uses a minimal number of power components—only six switches—to achieve a five-level output, resulting in a simple and cost-effective structure. Second, its inherent ground connection effectively eliminates common-mode leakage currents, a critical safety and performance requirement for grid-tied and off-grid photovoltaic systems. Third, the rear-end switched capacitor structure connected to the NPC neutral point helps to naturally balance the neutral-point voltage, mitigating a major drawback of conventional NPC topologies. The design also leads to lower voltage stress on all switches and reduced demands on the output filter components. The capacitor voltage is self-balanced, and the output waveform quality is exceptional, as evidenced by a simulated THD of less than 1% for various modulation indices. These characteristics make our proposed inverter an excellent candidate for high-performance applications where efficiency, reliability, and power quality are paramount. This work contributes a valuable new topology to the family of types of solar inverters, promising improved performance for the next generation of photovoltaic power conversion systems.