In modern photovoltaic (PV) power generation, solar inverters are the essential interface between the PV array and the utility grid. Among various types of solar inverter, the current source inverter (CSI) has drawn increasing attention due to its inherent boost capability, continuous input current, and fewer passive components compared to the widely used voltage source inverter (VSI). Both VSI and CSI are important types of solar inverter, yet they face distinct switching signal challenges. In VSI, dead-time is introduced to prevent shoot-through, while in CSI, overlap-time must be added to avoid open-circuit faults of the DC-link inductor. This paper focuses on the overlap-time phenomenon in current source grid-connected inverters, analyzing its effects on AC current quality and proposing an effective compensation strategy.
The topology of a typical current-source PV grid-connected inverter is shown in the following figure, which illustrates the key components: DC-side inductor \(L_{dc}\), six-switch inverter bridge with series diodes, LC filter, and grid connection. This structure is one of the most promising types of solar inverter for low-voltage PV applications because it can operate with a lower DC input voltage than the peak AC voltage.
1. Generation of Overlap-Time in CSI
The CSI requires that the DC link current never be interrupted. Therefore, when switching between vectors, a short period (overlap-time \(t_{ov}\)) is deliberately added during which both the outgoing and incoming switches in the same-phase leg are turned on simultaneously. This is analogous to dead-time in VSI but with opposite polarity. Figure below depicts the switching signals in sector I of a seven-segment SVPWM scheme. In sector I, commutation occurs among the lower switches (S₄, S₆, S₂). Without overlap-time, a brief open circuit would occur, causing destructive overvoltage across the DC inductor.
The overlap-time modifies the actual current vector from the commanded one. During \(t_{ov}\), the inverter side current deviates from the ideal value, leading to low-order harmonic distortion in both the inverter-side currents and grid-side currents.
2. Analysis of Overlap-Time Effect
2.1 Equivalent Circuit During Overlap-Time
Consider the commutation from zero vector I₇ to active vector I₁ in sector I. During the overlap, switches S₄ and S₆ are both on. The direction of \(i_{dc}\) depends on the relationship between capacitor voltages \(u_a\) and \(u_b\):
– If \(u_a > u_b\), diode D₄ continues conducting, D₆ is reverse-biased, and the current vector remains I₇, causing an error in \(i_a\) and \(i_b\).
– If \(u_a < u_b\), diode D₄ becomes reverse-biased, D₆ conducts, and commutation proceeds normally without error.
Similarly, for upper-side commutation (e.g., in sector II), the current will only flow through the switch connected to the lower capacitor voltage. A general rule emerges: during the overlap-time, the DC link current always flows through the phase with the highest voltage for lower-leg commutation, and through the phase with the lowest voltage for upper-leg commutation. If the commutation order is from high to low voltage (lower leg) or low to high voltage (upper leg), no error occurs; otherwise, an error appears.
2.2 Average Current Error per Carrier Cycle
For a given carrier period, the average error in inverter-side phase currents depends only on the relative magnitudes of the three-phase capacitor voltages, regardless of the sector in which the reference vector lies. Taking the case where \(u_a > u_b > u_c\) as an example, the errors are summarized in Table 1.
| Capacitor Voltage Order | \(\Delta i_a\) | \(\Delta i_b\) | \(\Delta i_c\) |
|---|---|---|---|
| \(u_a > u_b > u_c\) | \(-2f_s t_{ov} i_{dc}\) | 0 | \(2f_s t_{ov} i_{dc}\) |
| \(u_a > u_c > u_b\) | \(-2f_s t_{ov} i_{dc}\) | \(2f_s t_{ov} i_{dc}\) | 0 |
| \(u_b > u_a > u_c\) | 0 | \(-2f_s t_{ov} i_{dc}\) | \(2f_s t_{ov} i_{dc}\) |
| \(u_b > u_c > u_a\) | \(2f_s t_{ov} i_{dc}\) | \(-2f_s t_{ov} i_{dc}\) | 0 |
| \(u_c > u_a > u_b\) | 0 | \(2f_s t_{ov} i_{dc}\) | \(-2f_s t_{ov} i_{dc}\) |
| \(u_c > u_b > u_a\) | \(2f_s t_{ov} i_{dc}\) | 0 | \(-2f_s t_{ov} i_{dc}\) |
Where \(f_s\) is the carrier frequency and \(i_{dc}\) the DC link current. This table applies to the linear modulation region. In the over-modulation region or near zero-crossing of a phase current, the pattern slightly differs but the overall harmonic effect remains similar.
3. Harmonic Characteristics of Overlap-Time Current Error
The periodic error in phase current \(\Delta i_a\) can be approximated as a square wave switching between \(+2f_s t_{ov} i_{dc}\) and \(-2f_s t_{ov} i_{dc}\) every 60 electrical degrees. Using Fourier series expansion, we obtain:
\[
\Delta i_a = -\frac{4\sqrt{3}f_s t_{ov} i_{dc}}{\pi} \left[ \sin(\omega t) + \sum_{k=1}^{\infty} (-1)^k \left( \frac{\sin((6k-1)\omega t)}{6k-1} + \frac{\sin((6k+1)\omega t)}{6k+1} \right) \right]
\]
Equation (1) reveals that the overlap-time introduces predominantly \(6k \pm 1\) order harmonics (5th, 7th, 11th, 13th, …) into the inverter-side current. The amplitude of each harmonic is proportional to \(t_{ov}\) and \(i_{dc}\).
The transfer function from inverter-side current to grid-side current through the LC filter is:
\[
G_{i2ig}(s) = \frac{1}{LC s^2 + CR s + 1}
\]
With typical parameters \(L=4\,\text{mH}\), \(C=66\,\mu\text{F}\), \(R=0.5\,\Omega\), the filter has a resonant peak around 310 Hz. The 5th harmonic (250 Hz) and 7th harmonic (350 Hz) fall within the resonance region, thereby being amplified on the grid side. Consequently, the grid current exhibits significant 5th and 7th harmonic distortion when overlap-time is uncompensated.
4. Proposed Compensation Method
4.1 Overall Control Structure
The control system consists of an outer DC-link current loop and inner grid-current loop in the synchronous d-q reference frame. The compensation block inserts the calculated current errors \(\Delta i_d\), \(\Delta i_q\) into the current references, as illustrated in the block diagram of Fig. 11 (described in text). The key steps are:
1. Sample three-phase capacitor voltages \(u_a, u_b, u_c\);
2. Apply a high-precision digital filter to extract the fundamental component;
3. Look up Table 1 according to the relative magnitudes of the filtered voltages to obtain \(\Delta i_a,\Delta i_b,\Delta i_c\);
4. Transform to d-q frame to get \(\Delta i_d,\Delta i_q\);
5. Subtract \(\Delta i_d,\Delta i_q\) from the output of the current controllers before SVPWM.
4.2 Digital Filter for Capacitor Voltages
To avoid errors caused by switching ripples in capacitor voltages, we design a second-order digital band-pass filter centered at the fundamental frequency (50 Hz). Its z-domain transfer function is:
\[
G_R(z) = \frac{40\omega_n T_s (1 – z^{-2})}{40\omega_n^2 T_s^2 + 4\omega_n T_s + (2\omega_n T_s^2 – 4)z^{-1} + (40 – 40\omega_n T_s^2)z^{-2}}
\]
Where \(\omega_n = 100\pi\) rad/s and \(T_s\) is the sampling period. The filter accurately extracts the fundamental component with zero phase delay, as verified by simulation.
4.3 Compensation in d-q Frame
The current errors in the d-q frame are obtained by Park transformation of the three-phase errors. Then the compensated current references become:
\[
i_d^* = i_{d,ref} – \Delta i_d,\quad i_q^* = i_{q,ref} – \Delta i_q
\]
These modified references are fed into the SVPWM modulator. The effectiveness depends critically on the correct determination of the capacitor voltage order; hence the digital filter is indispensable.
5. Simulation and Experimental Verification
5.1 Simulation Results
A simulation model was built in MATLAB/Simulink with \(i_{dc}=15\,\text{A}\), \(f_s=10\,\text{kHz}\). Table 2 summarizes the inverter-side current harmonics under different overlap-times without compensation.
| \(t_{ov}\) (μs) | Fundamental (A) | 5th harm. (A) | 7th harm. (A) | THD (%) |
|---|---|---|---|---|
| 0 | 9.90 | 0.005 | 0.003 | 96.53 |
| 0.5 | 9.835 | 0.037 | 0.025 | 97.20 |
| 1 | 9.776 | 0.069 | 0.049 | 97.89 |
| 1.5 | 9.713 | 0.098 | 0.074 | 98.61 |
| 2 | 9.656 | 0.140 | 0.097 | 99.35 |
| 2.5 | 9.592 | 0.175 | 0.122 | 100.09 |
| 3 | 9.543 | 0.213 | 0.148 | 100.88 |
After applying the proposed compensation, the harmonics are dramatically reduced, as shown in Table 3. The fundamental amplitude recovers to near 9.9 A, and the THD stays almost unchanged from the no-overlap case.
| \(t_{ov}\) (μs) | Fundamental (A) | 5th harm. (A) | 7th harm. (A) | THD (%) |
|---|---|---|---|---|
| 0.5 | 9.897 | 0.005 | 0.003 | 96.55 |
| 1 | 9.896 | 0.009 | 0.005 | 96.56 |
| 1.5 | 9.896 | 0.017 | 0.009 | 96.57 |
| 2 | 9.890 | 0.028 | 0.018 | 96.57 |
| 2.5 | 9.890 | 0.041 | 0.027 | 96.57 |
| 3 | 9.876 | 0.068 | 0.049 | 96.65 |
5.2 Experimental Results
A laboratory prototype was built using a TMS320F28335 controller, with parameters identical to the simulation. For \(t_{ov}=3\,\mu\text{s}\) without compensation, grid current THD was 5.93% with 5th and 7th harmonics of 0.451 A and 0.356 A respectively. After applying the proposed compensation, the grid current THD dropped to 1.65%, and the 5th/7th harmonics reduced to 0.119 A and 0.097 A. The fundamental amplitude increased from 9.69 A to 9.95 A. These results confirm the effectiveness of the method.
To highlight the importance of the digital filter, an experiment with compensation but without the filter yielded a THD of 2.65%, proving that raw voltage samples cause misjudgment in the lookup table, degrading performance.
5.3 Comparison Under Low Switching Frequency
At a lower carrier frequency of 1 kHz, the proposed compensation still performs well, achieving a THD of 3.95% and 5th/7th harmonics of 1.58% and 1.29%. For comparison, a previously published stationary-frame compensation method (from [21]) resulted in 5.22% THD and higher harmonics, because the lower control frequency introduces angle errors in the Park transformation of the compensating signals.
6. Discussion
The proposed method works effectively for the linear modulation region. In the over-modulation region, the pattern of error changes: for example, when the zero-vector duty cycle becomes zero, only two overlap intervals exist per carrier cycle. However, the general principle of depending on capacitor voltage polarity remains, and the same lookup table can be applied with minor modifications. Moreover, dynamic performance is unaffected because the compensation is applied as a feedforward perturbation without altering the closed-loop poles.
7. Conclusion
This paper has thoroughly analyzed the overlap-time effect in current source grid-connected inverters, one of the critical types of solar inverter for renewable energy integration. The key findings are:
- The current error during overlap-time depends exclusively on the relative magnitudes of the three-phase capacitor voltages, not on the reference vector sector.
- Overlap-time reduces the fundamental component of inverter-side current and introduces 6k±1 harmonics, which are further amplified by the LC filter resonance, leading to significant 5th and 7th harmonics in grid current.
- A high-precision digital filter is essential to correctly extract the fundamental capacitor voltage, enabling accurate lookup of the error table.
- The proposed d-q frame compensation strategy effectively restores the fundamental current and suppresses low-order harmonics without compromising dynamic performance, as verified by simulation and experiments.
The proposed method is simple to implement and can be applied to all types of solar inverter based on current-source topology, improving grid current quality and system efficiency.