In my research on power electronics for renewable energy systems, I have focused on the modulation techniques for three-level inverters, which are widely used in grid-connected applications. Among the various types of solar inverter, the T-type three-level inverter has gained significant attention due to its high efficiency and low harmonic distortion. However, challenges such as common-mode voltage (CMV) suppression and neutral-point (NP) potential balancing remain critical. In this paper, I propose a hybrid discontinuous pulse width modulation (DPWM) strategy based on improved carrier implementation to address these issues simultaneously. The strategy not only reduces switching losses but also minimizes CMV ripples and ensures fast NP potential recovery.
The proposed method is particularly suitable for transformerless photovoltaic systems, where leakage current caused by CMV must be strictly limited. Compared to traditional two-level inverters, three-level topologies inherently produce lower CMV, but careful modulation design is still required. I aim to provide a comprehensive solution that leverages the benefits of DPWM while mitigating its drawbacks. My approach combines three specific DPWM types: DPWMA (with low CMV), DPWMMAX, and DPWMMIN, and implements them using an improved carrier scheme to achieve both low CMV ripple and NP balance. Detailed simulation and experimental results validate the effectiveness of the proposed strategy.
Before diving into the technical details, I briefly review the topology. The T-type three-level inverter (as shown in the figure below) consists of four switches per phase. Each phase can output three voltage levels: positive (P), zero (O), and negative (N).
This inverter is one of the common types of solar inverter used in medium-voltage grid-connected systems. The ability to produce three voltage levels reduces the dv/dt stress on the power devices and improves the output waveform quality compared to two-level inverters.
Common-Mode Voltage Analysis
The common-mode voltage is defined as the average of the three phase-to-neutral voltages:
$$
V_{CM} = \frac{V_{ao} + V_{bo} + V_{co}}{3}
$$
Depending on the switching states, the CMV can take values of 0, ±Vdc/6, ±Vdc/3, or ±Vdc/2. In traditional space vector PWM (SVPWM), vectors with large CMV (e.g., ±Vdc/3) are used, which exacerbates leakage current. The DPWM strategy known as DPWMA only utilizes vectors with CMV magnitudes of 0 or ±Vdc/6, thus reducing the maximum CMV by half. The selected vectors and clamping patterns for DPWMA are illustrated in the original text.
The zero-sequence voltage injection for DPWMA can be expressed as:
$$
v_{0|_{DPWMA}} = \min\left[\min(v_{xh}), \min(v_{xl})\right]
$$
where vxh and vxl are defined based on the original modulation waves. The final modulation waves are obtained by adding this zero-sequence component.
Hybrid DPWM for Neutral-Point Balancing
The NP potential is defined as:
$$
V_{np} = \frac{V_{C2} – V_{C1}}{2}
$$
where VC1 and VC2 are the voltages across the upper and lower DC-link capacitors. In steady state, DPWMA has a negligible effect on the NP potential over one fundamental cycle. However, if an initial NP offset exists, DPWMA alone cannot quickly balance it. To handle this, I introduce a hybrid scheme: when |Vnp| is within a threshold, DPWMA is used for low CMV and low switching loss; when the offset exceeds the threshold, DPWMMAX or DPWMMIN is applied to rapidly restore balance. DPWMMAX clamps the phase with the highest voltage to the positive bus (P state), causing a net outflow of charge from the NP, thereby raising Vnp. Conversely, DPWMMIN clamps the phase with the lowest voltage to the negative bus (N state), lowering Vnp.
The zero-sequence voltages for these two strategies are:
$$
v_{0|_{DPWMMAX}} = 1 – v_{max}
$$
$$
v_{0|_{DPWMMIN}} = -1 – v_{min}
$$
where vmax and vmin are the maximum and minimum of the original three-phase modulation waves. The switching between DPWMA and the balancing DPWMs is based on a hysteresis comparator. The flowchart of the proposed hybrid DPWM is shown in the original paper. This approach ensures fast NP recovery without increasing the overall CMV level significantly.
Improved Carrier Implementation to Reduce CMV Ripple
Even though DPWMA limits the CMV magnitude to ±Vdc/6, the CMV ripple (peak-to-peak variation within a switching period) can still be as high as Vdc/3 when conventional carrier-based PWM (CB-PWM) is used. The root cause lies in the switching sequence order. For example, in the region where phase a is clamped to P and phases b and c are clamped to O, the conventional carrier arrangement leads to sequences such as [PNN]→[PON]→[POO], resulting in CMV values of −Vdc/6, 0, and Vdc/6, giving a ripple of Vdc/3.
To mitigate this, I propose an improved carrier assignment strategy. The key idea is to arrange the carrier types (concave or convex) for the non-clamped phases in such a way that the switching transitions produce CMV variations only between 0 and either +Vdc/6 or −Vdc/6, but not both extremes within the same switching period. The carrier selection rule is summarized in Table 1 for different clamping regions.
| Clamping Region | Carrier Type for Non-Clamped Phases |
|---|---|
| Sx = O (x = a,b,c), with vx > 0 | Both use concave carrier |
| Sx = O (x = a,b,c), with vx < 0 | Both use convex carrier |
| Sa = P | Phase b: concave; Phase c: convex |
| Sa = N | Phase b: convex; Phase c: concave |
| Sb = P | Phase a: concave; Phase c: convex |
| Sb = N | Phase a: convex; Phase c: concave |
| Sc = P | Phase a: concave; Phase b: convex |
| Sc = N | Phase a: convex; Phase b: concave |
With this assignment, the CMV ripple is reduced to Vdc/6 in all regions. The improvement is achieved without increasing the switching frequency or altering the clamping pattern. This technique is applicable not only to DPWMA but also to DPWMMAX and DPWMMIN during the NP balancing phase, ensuring consistently low CMV ripple throughout the operation.
Simulation and Experimental Verification
I built a simulation model of a 10 kW T-type three-level grid-connected inverter with parameters listed in Table 5 of the original work. The DC bus voltage was 800 V, and the switching frequency was 20 kHz. I compared three modulation schemes: conventional SVPWM, conventional carrier-based DPWMA, and the proposed improved-carrier hybrid DPWM.
Simulation results under balanced NP: The phase-to-neutral voltages and CMV waveforms clearly show that conventional SVPWM produces a maximum CMV of Vdc/3 (≈267 V at 800 V DC). DPWMA reduces the maximum CMV to Vdc/6 (≈133 V). However, with the conventional carrier, the CMV ripple remains at Vdc/3. In contrast, the proposed improved carrier DPWMA achieves a ripple of only Vdc/6, i.e., half of the conventional method.
Simulation results for NP balancing: I initialized the NP potential at +50 V (upper capacitor higher). With only DPWMA, the NP remained unbalanced after 0.2 s. When the hybrid scheme was activated, the controller detected the offset, switched to DPWMMIN (which injects negative zero-sequence to lower Vnp), and the NP returned to zero within about 0.02 s (one fundamental cycle). After recovery, the system switched back to DPWMA. The CMV during the balancing transient was also reduced when using the improved carrier. Similarly, a negative initial offset of −50 V was corrected by DPWMMAX.
Experimental results: I carried out experiments on a laboratory prototype with reduced DC bus voltage (400 V) for safety, while maintaining the same modulation ratio (0.775). The results confirmed the simulation findings. Figure 10 shows the experimental CMV and phase current for the three schemes. The measured THD of the output current was 1.85% for SVPWM, 1.88% for conventional DPWMA, and 1.70% for the proposed improved-carrier DPWMA, indicating that the proposed method does not degrade current quality.
To verify NP balancing, I intentionally ran DPWMMIN for 40 ms to unbalance the NP. Figure 11 shows that with only DPWMA, the NP remained offset. Figure 12 demonstrates that with the hybrid strategy, the NP recovered within 20 ms after switching to DPWMMAX. The CMV during the transient was also captured; the improved carrier reduced the ripple from Vdc/3 to Vdc/6.
A quantitative comparison of the three modulation strategies is summarized in Table 2.
| Strategy | Maximum |CMV| | Minimum CMV Ripple | Current THD (%) |
|---|---|---|---|
| Conventional SVPWM | Vdc/3 | Vdc/2 | 1.85 |
| Conventional carrier DPWMA | Vdc/6 | Vdc/3 | 1.88 |
| Proposed improved-carrier hybrid DPWM | Vdc/6 | Vdc/6 | 1.70 |
Conclusion
In this work, I have presented a hybrid discontinuous PWM strategy for three-level inverters that effectively addresses both CMV suppression and NP potential balancing. The key contributions are:
- Low switching losses are achieved through the inherent clamping action of DPWM, which reduces the number of switching transitions per fundamental cycle.
- Common-mode voltage magnitude is limited to ±Vdc/6, half that of conventional SVPWM, by selecting only low-CMV vectors.
- Common-mode voltage ripple is further reduced to Vdc/6 through an improved carrier assignment that eliminates the simultaneous appearance of positive and negative CMV peaks within one switching period.
- Neutral-point potential is rapidly balanced by switching between DPWMA and DPWMMAX/DPWMMIN when an offset is detected. The balancing process is completed within one fundamental cycle without increasing CMV.
The proposed modulation technique is particularly well-suited for transformerless grid-connected inverters, where leakage current must be minimized. It can be implemented purely in the carrier domain, making it easy to integrate into existing digital controllers. The method is applicable to various types of solar inverter that employ three-level topologies, such as NPC and T-type inverters. Future work may extend the strategy to multilevel inverters or consider adaptive threshold optimization for NP balance.
Overall, the simulation and experimental results confirm the effectiveness of the proposed hybrid DPWM with improved carrier, demonstrating a significant improvement in CMV performance while maintaining low switching losses and good output quality.