In the context of modern distributed energy systems, the types of solar inverter have evolved significantly to meet the demands of high-power applications. As a critical power interface in new energy microgrids, the three-phase inverter provides stable voltage and frequency. However, the phase circulation issue within parallel inverter systems severely impacts power quality and conversion efficiency at the output side of the microgrid. To address this, a compound suppression strategy of phase circulation (CSSPC) based on sliding mode control (SMC) is proposed. This strategy effectively suppresses both inter-phase and intra-phase circulation, enhancing the robustness and output performance of the parallel system.
The types of solar inverter are diverse, ranging from string inverters to central inverters, and in low-voltage microgrids, parallel configurations are commonly employed to increase system power capacity and ensure operational reliability. In such systems, the inevitable differences in internal parameters and external actions among inverters lead to inter-phase and intra-phase circulation, collectively termed as phase circulation. These currents not only reduce system conversion efficiency but can also cause grid instability if their amplitude becomes excessive. Therefore, the development of efficient suppression strategies for parallel inverter systems has become a focal point of research.
In this work, we first analyze the generation mechanism of phase circulation in parallel systems. Based on the classification of inter-phase and intra-phase circulation, we establish mathematical models to describe their behavior. The suppression mechanisms for each type of circulation are then discussed. To mitigate inter-phase circulation, we improve upon the traditional virtual impedance droop control (VIDC) method by incorporating SMC into the design of a robust droop controller. This controller enhances the power-sharing accuracy of the parallel system by improving bus voltage response, droop loop output precision, and virtual inductance regulation. For intra-phase circulation, we design a zero-sequence voltage SMC suppressor that dynamically adjusts the action time of zero vectors in space vector pulse width modulation (SVPWM), thereby indirectly eliminating intra-phase circulation. Finally, simulation results demonstrate the effectiveness of the proposed CSSPC strategy.
1. Classification and Modeling of Phase Circulation
To design an effective suppression strategy, it is essential to understand the origin of phase circulation. In a typical parallel three-phase inverter system, the generation of circulation currents can be attributed to two main categories: inter-phase circulation and intra-phase circulation.
1.1 Inter-phase Circulation Analysis
Inter-phase circulation arises from voltage and power parameter mismatches between parallel inverter units. Consider a system with n parallel three-phase inverters. The system can be simplified into an equivalent circuit where each inverter is represented as an AC voltage source with internal impedance. The load voltage and currents can be derived using Kirchhoff’s laws.
Let the output current of each inverter be represented as:
$$ \dot{I}_{o,m} = \frac{\dot{U}_L}{2Z_L} \pm \frac{\dot{U}_1 – \dot{U}_2}{Z_{o,1} + Z_{o,2}} $$
The inter-phase circulation current Ic between two parallel inverters is defined as:
$$ \dot{I}_c = \frac{\dot{I}_{o,1} – \dot{I}_{o,2}}{2} = \frac{\dot{U}_1 – \dot{U}_2}{Z_{o,1} + Z_{o,2}} $$
This indicates that inter-phase circulation is caused by the voltage difference Δ . The magnitude of the circulating current depends on the equivalent output impedance. Ideally, if the load power is precisely shared among inverters according to their capacity ratios, inter-phase circulation can be indirectly suppressed.
1.2 Intra-phase Circulation Analysis
Intra-phase circulation occurs when the power devices in the same phase of different inverters operate asynchronously. This asynchronous behavior creates a zero-sequence voltage uz, which in turn generates a zero-sequence current iz. The intra-phase circulation iz flows through the path shown in the system diagram.
The zero-sequence current can be expressed as:
$$ i_{z}(s) = \frac{u_{z,1}(s) – u_{z,2}(s)}{\sum_{m=1}^{2} L_{e,km} s + \sum_{m=1}^{2} R_{l,km}} $$
The key to suppressing intra-phase circulation is to eliminate the zero-sequence voltage between the corresponding phases. This is achieved by controlling the duty cycles of the switching devices to ensure synchronous operation.
2. Design of CSSPC Strategy for Phase Circulation
The proposed CSSPC strategy consists of two main parts: a robust droop SMC controller for suppressing inter-phase circulation and a zero-sequence voltage SMC suppressor for suppressing intra-phase circulation. This section details the design and stability analysis of these controllers.
2.1 Robust Droop SMC Controller Design
Traditional virtual impedance droop control (VIDC) has limitations in accurately sharing reactive power, especially under varying line conditions. The robust droop SMC controller is designed to address these limitations by improving bus voltage tracking, reactive power loop response, frequency accuracy, and virtual impedance adaptation.
The controller architecture incorporates several sub-controllers, each designed using SMC to ensure fast response and strong robustness.
2.1.1 AC Bus Voltage Tracking SMC
The objective is to ensure that the AC bus voltage Us dynamically follows the rated value UN. The state variable is defined as:
$$ x_U = U_s – U_N $$
The sliding mode surface SU and control law uU are designed as:
$$ S_U = c_{U,1} x_U + \dot{x}_U + c_{U,2} \int x_U dx $$
$$ u_U = -\text{sgn}(S_U) $$
An exponential reaching law is used to ensure fast convergence:
$$ \dot{S}_U = -\varepsilon_U \text{sgn}(S_U) – k_U S_U $$
The stability of this controller is verified using the Lyapunov function:
$$ V_U = \frac{1}{2} S_U^2 $$
$$ \dot{V}_U = S_U \dot{S}_U = -\varepsilon_U |S_U| – k_U S_U^2 < 0 $$
2.1.2 Q-U Loop Voltage Response SMC
This sub-controller minimizes the deviation between the adjusted bus voltage Us‘ and the Q-U loop output UQ,m:
$$ x_E = U_s’ – U_{Q,m} $$
The sliding surface and control law are:
$$ S_E = c_{E,1} x_E + \dot{x}_E + c_{E,2} \int x_E dx $$
$$ u_E = -\text{sgn}(S_E) $$
The stability condition is:
$$ \dot{V}_E = -\varepsilon_E |S_E| – k_E S_E^2 |S_E| < 0 $$
The resulting Q-U control equation is:
$$ U_m(s) = (c_{E,1} + \frac{c_{E,2}}{s}) \left[ (c_{E,1} + \frac{c_{E,2}}{s}) (U_s(s) – U_N(s)) – N_m (Q_m(s) – Q_{N,m}(s)) \right] $$
2.1.3 P-f Loop Frequency Response SMC
The goal is to regulate the system output frequency fs to its rated value fN:
$$ x_f = f_s – f_N $$
The sliding surface and control law are:
$$ S_f = c_{f,1} x_f + \dot{x}_f + c_{f,2} \int x_f dx $$
$$ u_f = -\text{sgn}(S_f) $$
The P-f control equation is:
$$ f_m(s) = (c_{f,1} + \frac{c_{f,2}}{s}) (f_s(s) – f_N(s)) – M_m (P_m(s) – P_{N,m}(s)) $$
2.1.4 Adaptive Virtual Inductance Regulator
To address the limitations of fixed virtual inductance, an adaptive regulator is designed based on the error between the output current io,km and the grid-side current is,k:
$$ x_v = i_{o,km} – i_{s,k} $$
The sliding surface is:
$$ S_v = c_{v,1} x_v + \dot{x}_v + c_{v,2} \int x_v dx $$
The regulator adaptively adjusts the virtual inductance Xv,m, resulting in a modified Q-U control equation with voltage coefficient Nv,m:
$$ U_m(s) = (c_{E,1} + \frac{c_{E,2}}{s}) \left[ (c_{E,1} + \frac{c_{E,2}}{s}) (U_s(s) – U_N(s)) – (N_m + N_{v,m}(s)) Q_m(s) – N_m Q_{N,m}(s) \right] $$
2.2 Small Signal Stability Analysis
To ensure the stability of the proposed robust droop SMC controller under varying parameters, a small signal analysis is performed. The closed-loop characteristic equation for the system is derived as:
$$ a s^4 \tilde{\theta}_m + b s^3 \tilde{\theta}_m + c s^2 \tilde{\theta}_m + d s \tilde{\theta}_m + e = 0 $$
The stability of the system is evaluated by examining the root locus as key parameters change. The parameters used for the root locus analysis are given in the following table:
| Parameter | Description |
|---|---|
| cf,1 | Proportional gain for P-f loop frequency SMC |
| cE,1 | Proportional gain for Q-U loop voltage SMC |
| cf,2 | Integral gain for P-f loop frequency SMC |
| cE,2 | Integral gain for Q-U loop voltage SMC |
| εU | Reaching law gain for bus voltage SMC |
| kU | Reaching law gain for bus voltage SMC |
2.3 Zero-Sequence Voltage SMC Suppressor Design
The generation of zero-sequence voltage in SVPWM is the primary cause of intra-phase circulation. To suppress this, a regulation factor km is introduced to dynamically control the action time of zero vectors. This factor modifies the switching times of the inverter bridge arms, ensuring synchronous operation and eliminating the zero-sequence voltage.
The modulated switching times after introducing km are:
$$ T_{S,am}’ = T_{S,am} + k_m T_c $$
$$ T_{S,bm}’ = T_{S,am}’ + \frac{d_{1m}}{2} T_c $$
$$ T_{S,cm}’ = T_{S,bm}’ + \frac{d_{2m}}{2} T_c $$
The intra-phase circulation current is then re-expressed as:
$$ i_z(s) = \frac{U_{dc}}{\sum_{m=1}^{2} L_{e,km} s + \sum_{m=1}^{2} R_{l,km}} \left[ (d_{11} + 2d_{21} + \frac{3d_{01}}{2} – 6k_1) – (d_{12} + 2d_{22} + \frac{3d_{02}}{2} – 6k_2) \right] $$
A zero-sequence voltage SMC suppressor is designed to regulate km such that the zero-sequence voltage is minimized. The state variable is the intra-phase circulation current:
$$ x_z = i_z $$
The sliding mode surface Sz and control law uz are:
$$ S_z = c_{z,1} x_z + \dot{x}_z + c_{z,2} \int x_z dx $$
$$ u_z = -\text{sgn}(S_z) $$
3. Simulation Verification and Analysis
To validate the performance of the proposed CSSPC strategy, simulation experiments are conducted using a two-unit parallel three-phase inverter system. The controllers and system are modeled based on the parameters listed in the following tables.
| Parameter | Value | Parameter | Value |
|---|---|---|---|
| cU,1 | 10 | cE,2 | 0.001 |
| cU,2 | 0.1 | εE | 1 |
| εU | 0.5 | kE | 10 |
| kU | 1 | cf,1 | 300 |
| cE,1 | 0.001 | cf,2 | 500 |
| εf | 1 | kv | 5 |
| kf | 10 | cz,1 | 0.1 |
| cv,1 | 5 | cz,2 | 10 |
| cv,2 | 0.1 | εz | 0.01 |
| εv | 0.001 | kz | 0.1 |
| Parameter | Value | Parameter | Value |
|---|---|---|---|
| Input DC Voltage (Udc) | 700 V | Rated Load Reactive Power (QLN) | 600 var |
| Main Circuit Capacitor (C0m) | 1000 μF | Virtual Inductance Initial Value (Xv,m(0)) | 0.314 Ω |
| Bus Parasitic Inductance (Lsm) | 1.54 μH | Regulation Factor (km) Max/Min | 0.52 / 0.48 |
| Filter Capacitor (Cf,km) | 100 μF | P-f Loop Droop Coefficient (Mm) | 1×10-5 |
| Primary Filter Inductance (Lf,k1m) | 8 mH | Q-U Loop Droop Coefficient (Nm) | 1×10-5 |
| Secondary Filter Inductance (Lf,k2m) | 6 mH | Rated Switching Frequency | 10 kHz |
| Line Resistance (Rl) | 0.202 Ω | Rated Carrier Frequency | 10 kHz |
| Line Inductance (Ll) | 1.471 mH | Rated Voltage (UN) | 311 V |
The simulation compares the output performance of the proposed CSSPC strategy with that of the traditional VIDC strategy under identical conditions of load power changes. The key performance metrics include active power (Pm), reactive power (Qm), output frequency (fm), bus voltage (Um), inter-phase circulation (ic), and intra-phase circulation (iz,m). The results demonstrate the superior transient and steady-state performance of the CSSPC strategy.
The active power response under CSSPC shows a 66.7% reduction in initial convergence time and a 21.7% reduction in maximum overshoot compared to VIDC. The steady-state error is reduced by 84.8%. Similarly, the reactive power error is reduced by 37.3%. The inter-phase circulation coefficient is controlled to 1.49%, and the intra-phase circulation coefficient is limited to 0.72%, well within the industry standard of 5%.
The following table summarizes the performance comparison between the two strategies.
| Signal | Convergence Time (s) | Overshoot (%) | Response Time (s) | Steady-State Error | Circulation Coefficient (%) |
|---|---|---|---|---|---|
| Pm – VIDC | 0.036 | 8.374 | 0.034 | 129.214 W | – |
| Pm – CSSPC | 0.012 | 6.561 | 0.014 | 19.671 W | – |
| Qm – VIDC | 0.054 | 77.993 | 0.019 | 40.475 var | – |
| Qm – CSSPC | 0.015 | 39.373 | 0.013 | 25.362 var | – |
| ic – VIDC | – | 15.408 | – | 0.984 A | 7.69 |
| ic – CSSPC | – | 13.784 | – | 0.191 A | 1.49 |
| iz,m – VIDC | – | 10.956 | – | 0.782 A | 6.11 |
| iz,m – CSSPC | – | 9.121 | – | 0.093 A | 0.72 |
In conclusion, the proposed CSSPC strategy, developed for this type of solar inverter topology, demonstrates a significant improvement in power sharing accuracy and circulation suppression compared to traditional VIDC methods. The types of solar inverter that adopt this parallel architecture can benefit from enhanced efficiency and stability in low-voltage microgrid applications. The sliding mode control-based design provides a robust and responsive solution to the critical problem of phase circulation.
