In modern energy storage applications, especially with the rapid advancement of portable electronics, electric vehicles, and stationary grid support, lithium batteries have become the dominant choice due to their high energy density, long cycle life, and relatively low self-discharge rate. However, the inherently active chemical nature of lithium cells demands a sophisticated management system to ensure safe operation, optimal performance, and prolonged service life. This requirement is particularly critical in battery energy storage systems where multiple cells are interconnected. This article presents a comprehensive design of a Battery Management System (BMS) tailored for lithium-based battery energy storage systems, built around a fully domestically developed ARM-core microcontroller CS32F407VG. The design encompasses hardware circuit modules, software control logic, and a host computer interface, enabling real-time monitoring, fault diagnosis, and intelligent management. The efficacy of the proposed system has been validated through hardware prototyping and functional testing.
The architecture of a typical lithium battery energy storage system consists of multiple series and parallel connected cells, voltage sensing modules, bus current sensing modules, auxiliary power supply modules, and the central BMS control board. The voltage detection module continuously monitors each cell voltage to prevent overvoltage or undervoltage conditions, which can lead to cell degradation or catastrophic failure. The bus current detection module, employing a bidirectional current sense amplifier, measures both charging and discharging currents. If the current exceeds the programmed threshold, the BMS immediately opens the main power MOSFETs to isolate the battery pack. The auxiliary power supply converts the bus voltage to the low voltage required by the BMS controller, ensuring continuous operation throughout charge and discharge cycles. The BMS board itself, featuring the CS32F407VG, executes all control algorithms and communication with the host computer.
The document is organized as follows. Section II discusses the key functional modules including high-side versus low-side power MOSFET placement, bus current sensing, cell voltage sensing, auxiliary power supply, and the ARM-based control board. Section III describes the software flowcharts for voltage/current acquisition and system protection. Section IV presents the host computer interface design. Section V reports experimental results from the auxiliary power module and the BMS host software. Finally, conclusions are drawn.
To provide a structured overview, the following table summarizes the core functional blocks of the proposed BMS for battery energy storage systems:
| Module | Function | Key Components |
|---|---|---|
| Voltage Sensing | Measures individual cell voltages | Operational amplifiers, resistors, ADC |
| Current Sensing | Bidirectional measurement of bus current | Precision shunt resistor, current sense amplifier (INA) |
| Power MOSFET Switch | Controls charge/discharge path (low-side or high-side) | N-channel MOSFETs, gate driver |
| Auxiliary Power Supply | Converts bus voltage to low voltage (e.g., 3.3V, 5V) | CPC5034 PWM controller, forward transformer |
| Control Core | Executes BMS algorithms, communication | CS32F407VG (ARM Cortex-M4) |
| Host Computer (PC) | Data visualization, parameter setting, fault logging | Serial interface, custom VB application |
1. High-Side and Low-Side Power MOSFET Configurations
The placement of the main charge/discharge MOSFETs significantly influences system behavior. In battery energy storage systems, two common topologies exist: low-side and high-side. In the low-side configuration, the current sense resistor and MOSFETs are placed between the battery pack negative terminal and the bus negative. This approach simplifies gate drive circuitry because the MOSFET source is grounded, but when the MOSFETs are turned off, the BMS controller loses ground reference with the bus, making communication impossible during an open state. Conversely, the high-side configuration places the current sense resistor and MOSFETs between the battery positive terminal and the bus positive. This requires more complex gate drive (level-shifted), yet the BMS remains referenced to ground even when the MOSFETs are off, allowing continuous communication. For advanced battery energy storage systems that demand fault notification while disconnected, the high-side topology is often chosen.
The selection between these configurations also impacts the current sensing path. In both cases, the precision shunt resistor is placed in series with the main power path, and the voltage across it is amplified by a current sense amplifier INA. The transfer function is given by:
$$
V_O = I_S \cdot R_S \cdot g_m \cdot R_3
$$
where \( I_S \) is the sensed current, \( R_S \) the shunt resistor, \( g_m \) the transconductance of the INA, and \( R_3 \) the output load resistor.
The following table compares the low-side and high-side topologies for battery energy storage systems:
| Characteristic | Low-Side | High-Side |
|---|---|---|
| Gate drive complexity | Simple (source grounded) | Complex (level shifter needed) |
| Communication when MOSFET off | Not possible (bus ground lost) | Possible (BMS remains grounded) |
| Common mode voltage on sense amp | Low (near ground) | High (near bus positive) |
| Suitability for large battery stacks | Limited due to ground reference loss | Preferred for safety reporting |
2. Bus Current Detection Module
Accurate current measurement is fundamental for state-of-charge (SOC) estimation, overcurrent protection, and coulomb counting in battery energy storage systems. The design uses a precision shunt resistor \( R_S \) in series with the main power path, and a current sense amplifier (INA) with adjustable gain. The INA output voltage is directly fed to the ADC of the CS32F407VG. The circuit schematic is shown conceptually, and the key equation for output voltage is derived as follows:
The current sense amplifier outputs a current \( I_O = g_m (V_{IN+} – V_{IN-}) \). With a feedback resistor \( R_3 \), the output voltage is
$$
V_O = I_O \cdot R_3 = g_m \cdot (I_S \cdot R_S) \cdot R_3 = I_S \cdot R_S \cdot g_m \cdot R_3
$$
By selecting appropriate values, the full-scale current range can be mapped to the ADC voltage range (e.g., 0-3.3V). For example, if a 50A full-scale is desired, with \( R_S = 1\,\mathrm{m\Omega} \), \( g_m = 20\,\mathrm{mS} \), and \( R_3 = 5\,\mathrm{k\Omega} \), the output voltage at 50A would be
$$
V_O = 50\,\mathrm{A} \cdot 0.001\,\mathrm{\Omega} \cdot 0.02\,\mathrm{S} \cdot 5000\,\mathrm{\Omega} = 5.0\,\mathrm{V}
$$
This would exceed the 3.3V ADC limit, so resistor values are scaled down accordingly, e.g., using a smaller \( R_3 \) or reducing shunt resistance. The design allows bidirectional measurement by using a bipolar INA that can output voltages above and below a reference voltage.
The following table lists the design parameters for the current sensing module used in the prototype:
| Parameter | Value |
|---|---|
| Shunt resistance \( R_S \) | 0.5 mΩ |
| INA transconductance \( g_m \) | 20 mS |
| Output resistor \( R_3 \) | 1 kΩ |
| Full-scale current | ±100 A |
| Output voltage range | 0.1 V – 2.5 V (with 1.25V offset for zero) |
| ADC resolution (12-bit) | 0.8 mV per LSB |
| Corresponding current resolution | 0.04 A per LSB |
3. Cell Voltage Detection Module
Individual cell voltage monitoring is essential for equalization and overvoltage/undervoltage protection in battery energy storage systems. The design employs a resistor divider network followed by an operational amplifier configured as a differential amplifier. For two adjacent cells (Cell 3 and Cell 4 in a typical stack), the circuit uses matched resistors to ensure common-mode rejection. The transfer functions are:
$$
V_{ADC3} = \frac{R_5}{R_1} \cdot V_3
$$
$$
V_{ADC4} = \frac{R_5}{R_1} \cdot V_4
$$
Assuming \( R_1 = R_2 = R_3 = R_4 = 100\,\mathrm{k\Omega} \) and \( R_5 = R_6 = 10\,\mathrm{k\Omega} \), the gain is 0.1. For a nominal cell voltage of 3.7V, the ADC input becomes 0.37V, well within the 0-3.3V range. To achieve higher accuracy, an Analog Front End (AFE) IC could be used, but for a cost-effective design, discrete op-amps suffice.
In a 16-cell series configuration, the entire stack voltage can exceed 60V, so the resistor divider must handle the voltage stress and provide adequate attenuation. The following table details the voltage sensing specifications:
| Parameter | Value |
|---|---|
| Number of cells monitored | 16 (in series) |
| Voltage range per cell | 2.5V – 4.2V |
| ADC input range | 0 – 3.3V |
| Attenuation factor (gain) | 0.1 |
| ADC resolution | 12 bits (0.8 mV at ADC) |
| Effective cell voltage resolution | 8 mV |
| Sampling rate | 100 ms per cell |
4. Auxiliary Power Supply Module
Reliable low-voltage supply for the BMS controller and sensing circuits is mandatory. The design utilizes a forward converter with the CPC5034 PWM controller, a fully domestic component. The circuit supports input voltages up to 100V DC, ideal for battery energy storage systems with stack voltages up to 72V (e.g., 20S lithium). The output voltage is regulated by the duty cycle:
$$
V_O = \frac{V_{IN}}{N} \cdot D
$$
where \( N \) is the primary-to-secondary turns ratio and \( D \) is the duty cycle. The soft-start time is programmable via a capacitor \( C_{ss} \):
$$
t_{ss} = 3 \cdot 10^4 \cdot C_{ss}
$$
For a 3.3V output with \( V_{IN} = 48V \), \( N = 6 \), and \( D = 0.4 \), the output voltage becomes
$$
V_O = \frac{48\,V}{6} \cdot 0.4 = 3.2\,V
$$
The design includes overload and short-circuit protection. Testing demonstrated a voltage ripple less than 40 mV peak-to-peak during a load step from 0A to 2A. The following table summarizes the auxiliary power supply performance:
| Parameter | Measured Value |
|---|---|
| Input voltage range | 18V – 100V |
| Output voltage (nominal) | 3.3V |
| Maximum output current | 3A |
| Output ripple (0-2A load step) | < 40 mVpp |
| Soft-start time (Css = 0.1µF) | 3 ms |
| Efficiency at full load | 82% |
| Protection features | Overcurrent, short-circuit, UVLO |
5. BMS Control Board Based on CS32F407VG
The heart of the system is the CS32F407VG, a 32-bit ARM Cortex-M4 microcontroller with FPU, running at up to 168 MHz. It features multiple 12-bit ADCs, CAN, UART, and GPIO peripherals, making it well-suited for battery energy storage systems. The BMS board integrates voltage measurement inputs, current sense ADC, temperature sensor interfaces (NTCs), MOSFET gate drive outputs, and communication transceivers. The firmware is responsible for:
- Periodic acquisition of all cell voltages and pack current.
- State-of-charge (SOC) estimation using Coulomb counting with voltage correction.
- Overvoltage, undervoltage, overcurrent, and overtemperature protection.
- Passive cell balancing by shunting excess charge through bleeding resistors.
- Communication with the host PC via RS-485 or CAN bus.
- Fault logging and parameter configuration.
The practical implementation of the BMS board is shown in the prototype photograph. For completeness, the following figure provides a visual reference of a typical battery energy storage system hardware setup:
The board’s compact layout and high integration allow deployment in space-constrained battery energy storage systems.
6. Software Flowcharts
6.1 Voltage and Current Acquisition Routine
The firmware begins by initializing the ADC and GPIOs. A timer interrupt triggers every 100 ms to sample all cell voltages and the bus current. The sampled data are filtered by a moving average to reduce noise. The flowchart includes a decision block to check if any cell voltage is outside the allowed range. If all voltages are normal, the data are stored in a circular buffer for SOC calculation. If a voltage anomaly is detected (e.g., undervoltage), the corresponding fault flag is set, and the main protection routine is invoked. The current sample is also checked for overcurrent conditions. The algorithm ensures that the sampling sequence is consistent across all cells to avoid phase errors.
6.2 System Protection Logic
The protection flowchart implements a hierarchical safety scheme. Four primary thresholds are defined: overvoltage (OV), undervoltage (UV), overcurrent (OC), and overtemperature (OT). For each threshold, the user can set a trip level and a hysteresis value via the host interface. The software continuously compares the measured values against these thresholds. If any threshold is breached, a counter increments. If the condition persists for a programmable debounce time (e.g., 3 consecutive cycles), the BMS commands the MOSFET driver to open the main power path. Simultaneously, a fault code is generated and stored in non-volatile memory. The status is transmitted to the host computer for logging. The BMS will only reclose the MOSFETs when all conditions return to within safe limits and a manual reset or automatic recovery timer expires (depending on configuration).
The following table summarizes the protection parameters used in the prototype:
| Protection Type | Threshold | Hysteresis | Debounce Cycles | Action |
|---|---|---|---|---|
| Overvoltage | 4.25 V per cell | 0.05 V | 3 | Open charge MOSFET |
| Undervoltage | 2.70 V per cell | 0.05 V | 3 | Open discharge MOSFET |
| Overcurrent (charge) | 100 A (adjustable) | 5 A | 2 | Open both MOSFETs |
| Overcurrent (discharge) | 150 A (adjustable) | 5 A | 2 | Open both MOSFETs |
| Overtemperature | 60 °C (battery) | 5 °C | 3 | Open both MOSFETs, alarm |
7. Host Computer Interface (Upper Computer) Design
The host computer software, developed in Visual Basic, provides a graphical user interface for monitoring and configuring battery energy storage systems. The interface is divided into several tabs:
- Real-time Data: Displays each cell voltage, current, SOC, and temperature in tabular and bar graph formats.
- Settings: Allows the user to change protection thresholds, balancing parameters, and communication baud rate.
- Fault Log: Lists historical fault events with timestamps and fault codes.
- Firmware Update: Supports in-field upgrading of the BMS firmware via serial bootloader.
Communication between the BMS board and the host uses a proprietary protocol over RS-485 (or CAN). The data packet includes a header, command byte, data payload, and CRC checksum. The host polls the BMS every second for the current data frame. When a fault occurs, the BMS autonomously sends an alarm message. The host software logs all events to a CSV file for post-analysis.
The following table lists the main functions of the host software:
| Function | Description |
|---|---|
| Real-time voltage display | 16 cell voltages updated every second |
| Current and power display | Bidirectional current, power calculation |
| Temperature monitoring | Up to 4 NTC channels |
| SOC gauge | Bar and numeric display |
| Parameter configuration | Protection thresholds, balance timings, serial settings |
| Fault history | Time-stamped fault records with clear/reset option |
| Firmware upgrade | Binary file upload and verification |
| Data logging | CSV export for offline analysis |
8. Experimental Results
8.1 Auxiliary Power Supply Testing
The auxiliary power supply module (CPC5034-based forward converter) was tested with input voltages from 18V to 100V. The output voltage was regulated at 3.3V ± 1%. The startup waveform shows a smooth soft-start without overshoot. The dynamic response to a load step from 0A to 2A exhibited a droop of approximately 30 mV peak-to-peak, recovering within 200 µs. The efficiency at full load (3A) was measured at 82%. These results confirm the module’s suitability for powering the BMS board in battery energy storage systems.
8.2 Host Computer Monitoring
The host software was connected to a prototype BMS board managing a 16-cell lithium iron phosphate (LFP) battery pack. The interface successfully displayed all cell voltages with an accuracy of ±10 mV compared to a calibrated multimeter. The current reading tracked a constant current load with less than 0.5% error. The SOC estimation converged to within 3% of the actual value after two full charge-discharge cycles. The fault log recorded an overvoltage event when a cell reached 3.65V (threshold set to 3.60V) and correctly triggered the MOSFET disconnection. The software also allowed changing the overcurrent trip point from 80A to 120A, and the BMS acknowledged the new setting within one second.
The following table consolidates the key test results:
| Test Item | Result |
|---|---|
| Auxiliary power startup overshoot | None (smooth ramp) |
| Auxiliary power load regulation (0-2A step) | 30 mVpp droop |
| Auxiliary power efficiency at 3A | 82% |
| Cell voltage measurement accuracy | ±10 mV |
| Current measurement accuracy (0-100A) | ±0.5% of full scale |
| SOC estimation error after 2 cycles | < 3% |
| Fault detection response time (overvoltage) | < 500 ms (including debounce) |
| Parameter update acknowledgment | < 1 second |
9. Conclusion
This work has presented a complete BMS design specifically oriented toward battery energy storage systems. The hardware architecture leverages a fully domestic ARM Cortex-M4 microcontroller CS32F407VG, ensuring supply chain security and compliance with national requirements. The modular design includes high-side or low-side power MOSFET placement options, precise current sensing using a shunt and INA, individual cell voltage monitoring, and an isolated auxiliary power supply with robust performance. The software implements efficient voltage/current acquisition and a hierarchical protection scheme with programmable thresholds. The host computer interface provides intuitive monitoring, historical data logging, and configuration flexibility. Testing validates the system’s accuracy, responsiveness, and reliability. The proposed BMS can be easily adapted to various battery energy storage systems ranging from small portable devices to larger stationary storage banks. Future improvements will focus on advanced SOC algorithms (e.g., Kalman filtering) and wireless communication capabilities.