In the context of global energy shortage and the urgent need for green and low-carbon development, solar power generation has emerged as a key renewable energy solution. Grid-connected solar photovoltaic systems rely on inverters for energy conversion, and the performance of the inverter directly determines the efficiency of energy utilization. Among various inverter topologies, multilevel inverters have attracted significant research interest due to their advantages such as high voltage gain, low total harmonic distortion (THD), reduced filter size, and multiple output voltage levels. However, traditional multilevel inverters often suffer from complex structures, excessive power device counts, and high losses. To address these issues, this paper studies the widely used switched capacitor inverter topology and proposes a novel single-input expandable switched capacitor multilevel solar inverter. The proposed topology features reduced total device count, simpler structure, lower cost, low total voltage stress, and inherent capacitor voltage self-balancing. Compared with conventional multilevel inverters, the proposed solar inverter achieves four times voltage boost and multiple voltage level outputs with simple control, making it suitable for grid-connected photovoltaic applications. Furthermore, the topology is extendable: by adding a few additional components, a seventeen-level output with eight times voltage boost can be realized. The superiority of the proposed switched capacitor solar inverter is validated through experimental results.
Proposed Topology and Operating Principle
Topology Structure
The main circuit of the proposed switched capacitor solar inverter is shown in the figure below. The front-end switched capacitor unit consists of a DC input voltage source \(U_{dc}\), two capacitors \(C_1\) and \(C_2\), switches \(S_5\) to \(S_9\), and two diodes \(D_1\) and \(D_2\). By combining the DC source and capacitors in series/parallel configurations, four positive voltage levels are generated: \(U_{dc}\), \(2U_{dc}\), \(3U_{dc}\), and \(4U_{dc}\). The back-end H-bridge composed of switches \(S_1\) to \(S_4\) is responsible for polarity inversion and zero-level generation. Overall, the proposed nine-level solar inverter requires only one DC source, two capacitors, nine switches, and two diodes, producing nine output voltage levels: \(\pm 4U_{dc},\ \pm 3U_{dc},\ \pm 2U_{dc},\ \pm U_{dc},\ 0\). This structure significantly simplifies the circuit and reduces cost compared to existing topologies.
Operating States
The proposed solar inverter can operate in ten distinct states within one fundamental cycle to generate the nine required voltage levels. The following table summarizes the switching states, capacitor charging/discharging conditions, and the corresponding output voltage. In the table, “1” indicates the switch is ON, “0” indicates OFF; “C” denotes capacitor charging, “D” denotes discharging, and “-” denotes floating.
| State | Output Level | S1 | S2 | S3 | S4 | S5 | S6 | S7 | S8 | S9 | D1 | D2 | C1 | C2 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | \(+4U_{dc}\) | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | D | D |
| 2 | \(+3U_{dc}\) | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | C | D |
| 3 | \(+2U_{dc}\) | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | D | C |
| 4 | \(+U_{dc}\) | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | C | – |
| 5 | \(0^{+}\) | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | – | – |
| 6 | \(0^{-}\) | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | – | – |
| 7 | \(-U_{dc}\) | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | C | – |
| 8 | \(-2U_{dc}\) | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | D | C |
| 9 | \(-3U_{dc}\) | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | C | D |
| 10 | \(-4U_{dc}\) | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | D | D |
The detailed current paths for each state are described as follows (assuming resistive load). For state 1 (\(+4U_{dc}\)), switches \(S_1\), \(S_4\), \(S_6\), \(S_7\) conduct; the DC source and capacitors \(C_1\), \(C_2\) are connected in series, delivering \(4U_{dc}\) to the load. For state 2 (\(+3U_{dc}\)), \(S_1\), \(S_4\), \(S_6\), \(S_8\) and diode \(D_1\) conduct; the source and \(C_1\) (charging) are connected in series with \(C_2\) (discharging), outputting \(3U_{dc}\). For state 3 (\(+2U_{dc}\)), \(S_1\), \(S_4\), \(S_5\), \(S_7\), \(S_9\) and diode \(D_2\) conduct; the source and \(C_1\) (discharging) are in series and parallel to \(C_2\) (charging). For state 4 (\(+U_{dc}\)), \(S_1\), \(S_4\), \(S_5\), \(S_8\) and diode \(D_1\) conduct; only the DC source supplies the load while \(C_1\) charges and \(C_2\) floats. For the zero-level states (5 and 6), the H-bridge short-circuits the load; capacitors float. The negative half-cycle states are symmetric with corresponding switching patterns.
Modulation Strategy and Capacitor Analysis
Phase-Disposition PWM
To generate the required switching signals for the nine switches, a phase-disposition pulse width modulation (PDPWM) scheme is adopted. Four triangular carriers with amplitude \(A_c\) and frequency \(f_c\) are stacked vertically. A sinusoidal reference waveform with amplitude \(A_{ref}\) and fundamental frequency \(f\) is compared with these carriers to produce five raw pulse trains \(g_0\) to \(g_4\). The modulation index \(M_a\) is defined as:
$$M_a = \frac{A_{ref}}{4A_c}$$
The nine driving signals \(u_1\) to \(u_9\) are obtained through logic combinations of these raw pulses. The logic expressions are:
$$u_1 = g_0 + g_1 + g_2 + g_3 + g_4, \quad u_2 = \overline{g_0 + g_1 + g_2 + g_3 + g_4}$$
$$u_3 = g_4 + g_3 + g_2 + g_1, \quad u_4 = g_0 + g_1 + g_2$$
$$u_5 = g_4 + g_3, \quad u_6 = g_4 + g_2 + g_0$$
$$u_7 = g_3 + g_1, \quad u_8 = g_2 + g_0$$
$$u_9 = g_2 + g_0$$
The resulting gating signals ensure proper operation of the solar inverter across all nine levels. The carrier frequency is set to 10 kHz, and the modulation index is typically 0.9 for nine-level operation.
Capacitor Voltage Self-Balancing
One of the key advantages of the proposed solar inverter is that the capacitor voltages balance automatically without any auxiliary control. As shown in the operating table, during state 4, capacitor \(C_1\) charges from the source while \(C_2\) is floating. During state 3, \(C_1\) discharges and supplies energy together with the source to charge \(C_2\) to \(2U_{dc}\). During state 2, \(C_1\) charges and the source together with \(C_2\) (discharging) deliver \(3U_{dc}\). During state 1, both capacitors discharge. This natural charge/discharge profile maintains \(C_1\) at \(U_{dc}\) and \(C_2\) at \(2U_{dc}\) over a fundamental cycle.
Capacitor Design
The capacitor voltage ripple directly affects the output quality. The required capacitance can be derived from the maximum charge variation during the longest discharge interval. For capacitor \(C_2\), the most severe discharge occurs in the positive half-cycle between angles corresponding to \(3U_{dc}\) and \(4U_{dc}\). The discharge time instants \(t_3\) and \(t_4\) are calculated as:
$$t_3 = \frac{\sin^{-1}(3A_{ref}/A_{ref})}{2\pi f_{ref}} = \frac{\sin^{-1}(3)}{2\pi f_{ref}} \quad \text{(but since 3>1, it is actually limited by the carrier amplitude; in practice we use the actual reference voltage ratio)}$$
More precisely, with \(M_a=0.9\) and four carriers, the angles where the reference crosses the carrier levels are determined by the modulation scheme. For simplicity, the maximum charge discharged from \(C_2\) during the interval \([t_3, t_4]\) is:
$$\Delta Q_{21} = \int_{t_3}^{t_4} i_o \sin(2\pi f_{ref} t – \varphi) dt$$
where \(i_o\) is the load current amplitude and \(\varphi\) is the phase angle. Considering the worst-case scenario and ignoring any intermediate charging, the total discharge \(\Delta Q_2\) is obtained. The required capacitance is then:
$$C_2 \ge \frac{\Delta Q_2}{\Delta U_2}$$
With a allowed ripple \(\Delta U_2 = 10\%\) of the nominal voltage \(2U_{dc}\), and typical parameters, \(C_2\) is selected as 4700 μF. Similarly, \(C_1\) is designed for 5% ripple (\(\Delta U_1 = 5\%\) of \(U_{dc}\)), resulting in 6800 μF. Both capacitors have sufficient voltage margins.
Loss Analysis and Topology Comparison
Power Loss Breakdown
The total loss of the proposed solar inverter comprises three components: switching loss \(P_S\), conduction loss \(P_C\), and capacitor ripple loss \(P_R\). Switching loss occurs during turn-on and turn-off transitions of each switch. For a switch with turn-on time \(t_{on}\) and turn-off time \(t_{off}\), the energy losses are:
$$E_{on} = \frac{1}{6} U_S I_{S,on} t_{on} f_S, \quad E_{off} = \frac{1}{6} U_S I_{S,off} t_{off} f_S$$
Summing over all nine switches yields the total switching loss \(P_S\).
Conduction loss depends on the on-resistance of switches (\(r_S\)), diode resistance (\(r_D\)), and capacitor ESR (\(r_C\)). The equivalent parasitic resistance for each output level is listed in the following table.
| Output Level | Equivalent Resistance |
|---|---|
| 0 | \(4r_D + 2r_S\) |
| \(\pm U_{dc}\) | \(2r_D + 2r_S\) |
| \(\pm 2U_{dc}\) | \(r_D + 3r_S + r_C\) |
| \(\pm 3U_{dc}\) | \(r_D + 3r_S + r_C\) |
| \(\pm 4U_{dc}\) | \(4r_S + 2r_C\) |
The conduction loss is computed by integrating the instantaneous power over one fundamental cycle. For example, during the interval when the output level switches between 0 and \(+U_{dc}\), the energy loss is:
$$E_{0\&1VIN} = \int_{0}^{t_1} i_o^2(t) \cdot R_{eq}(t) dt$$
where \(R_{eq}(t)\) varies with the modulation signal. The total conduction loss \(P_C\) is obtained by summing contributions from all transition intervals and multiplying by the fundamental frequency.
Capacitor ripple loss arises from the voltage ripple across each capacitor. For a capacitor with ripple \(\Delta U_{ripple}\) and capacitance \(C\), the ripple power loss is approximately:
$$P_R = f_{ref} C (\Delta U_{ripple})^2$$
Using parameters \(r_S=0.27\ \Omega\), \(r_D=0.05\ \Omega\), \(r_C=0.03\ \Omega\), \(t_{on}=t_{off}=58\ ns\), \(f_S=10\ kHz\), and \(\Delta U_{ripple}=5\%\), the calculated total loss yields an efficiency of 98.77% at rated power, and above 94% for loads up to 2.5 kW.
Comparison with Other Topologies
To demonstrate the advantages of the proposed solar inverter, Tables 5 and 6 compare it with existing nine-level and seventeen-level inverters in terms of number of switches (\(N_{switch}\)), gate drivers (\(N_{driver}\)), diodes (\(N_{diode}\)), capacitors (\(N_{cap}\)), total standing voltage (TSV) normalized by the step voltage \(U_{step}\), cost function (CF), and voltage gain (G).
| Topology Reference | \(N_{sw}\) | \(N_{dr}\) | \(N_{diode}\) | \(N_{cap}\) | TSV (\(\times U_{step}\)) | CF | G |
|---|---|---|---|---|---|---|---|
| [12] | 9 | 8 | 2 | 2 | 30 | 51 | 2 |
| [13] | 10 | 10 | 3 | 2 | 25 | 50 | 4 |
| [14] | 8 | 8 | 3 | 3 | 26 | 48 | 4 |
| [15] | 10 | 8 | 6 | 3 | 28 | 55 | 4 |
| Proposed | 9 | 9 | 2 | 2 | 25 | 47 | 4 |
As seen in Table 5, the proposed solar inverter achieves the highest voltage gain (4×) with only two capacitors, two diodes, and nine switches. Its TSV is the lowest among the compared designs, and the cost function (CF = \(N_{sw}+N_{dr}+N_{diode}+N_{cap}+TSV\)) is also minimal at 47, indicating superior component utilization and reduced overall cost.
| Topology Reference | \(N_s\) | \(N_{cap}\) | TSV (\(\times U_{step}\)) | PIV | Gain |
|---|---|---|---|---|---|
| [16] | 26 | 7 | 95 | 8E | 8 |
| [17] | 24 | 8 | 53 | 8E | 8 |
| [18] | 20 | 5 | 52 | 8E | 8 |
| [19] | 19 | 4 | 53 | 6E | 6 |
| Proposed (extended) | 15 | 3 | 42 | 8E | 8 |
For the seventeen-level extended version, the proposed topology requires only 15 switches and 3 capacitors, achieving eight times voltage gain with a TSV of only 42 (vs. 52–95 in other works). This demonstrates the exceptional scalability and efficiency of the proposed solar inverter structure.
Experimental Verification
Nine-Level Prototype
An experimental prototype of the nine-level solar inverter was built with parameters listed in Table 7. The DC input voltage was set to 30 V, and the load was a 100 Ω resistor. The switching frequency was 10 kHz, and the modulation index was varied between 0.2 and 0.9 to demonstrate level transitions.
| Parameter | Value |
|---|---|
| DC Voltage | 30 V |
| Capacitors \(C_1\), \(C_2\) | 6800 μF, 4700 μF |
| Load Resistor \(R_o\) | 100 Ω |
| Carrier Frequency \(f_c\) | 10 kHz |
| Modulation Index \(M\) | 0.9, 0.6, 0.4, 0.2 |
| Switches/Diodes | IRFP460 / SDURK2060 |
When the modulation index was abruptly changed every 40 ms, the output voltage waveforms smoothly transitioned between the corresponding number of levels. The filtered output voltage and current remained sinusoidal with low distortion. Capacitor voltages were measured as shown in the next sub-figures: \(C_1\) stabilized at 30 V and \(C_2\) at 60 V, confirming self-balancing without external control.
Seventeen-Level Prototype
To validate the scalability, a seventeen-level solar inverter prototype was also constructed with one additional switch module and capacitor (\(C_3 = 2200\ \mu F\)). The DC input was set to 10 V for safety. Capacitor voltages \(C_1\), \(C_2\), and \(C_3\) were measured at 10 V, 20 V, and 40 V respectively, demonstrating perfect self-balancing. With modulation index \(M_a = 0.9\), the output exhibited seventeen distinct levels with eight times voltage boost (peak 80 V). Dynamic tests with modulation index changes showed smooth transitions between fifteen, thirteen, and eleven levels, confirming the flexibility of the proposed solar inverter for applications with varying voltage requirements.
Summary of Experimental Results
The experimental waveforms confirm that the proposed solar inverter operates correctly under all tested conditions. The capacitor voltages remain balanced within the designed ripple limits (5% for \(C_1\), 10% for \(C_2\) and \(C_3\)). The THD of the filtered output voltage is low, and the efficiency matches the theoretical predictions. These results validate the theoretical analysis and demonstrate the practical viability of the proposed single-input expandable switched capacitor multilevel solar inverter.
Conclusion
This paper has presented a novel single-input expandable switched capacitor multilevel solar inverter topology. The nine-level version uses only two capacitors, nine switches, and two diodes to achieve four times voltage boost and nine output levels. The topology features inherent capacitor voltage self-balancing and requires no complex control. The design is scalable: by adding one capacitor and four switches per level extension, a seventeen-level inverter with eight times boost is realized. Detailed operating principles, a phase-disposition PWM modulation scheme, capacitor design guidelines, and loss analysis have been provided. Comprehensive comparisons with existing multilevel inverters show that the proposed solar inverter offers superior component utilization, lower total voltage stress, and higher voltage gain. Experimental results from both nine-level and seventeen-level prototypes confirm the theoretical claims, demonstrating smooth level transitions, balanced capacitor voltages, and high-quality output waveforms. The proposed solar inverter is an attractive solution for grid-connected photovoltaic systems, especially where high voltage gain, low cost, and simple control are desired.