In recent years, the integration of photovoltaic (PV) systems into the power grid has gained significant momentum due to the growing demand for renewable energy sources. Among various components, the solar inverter plays a critical role in converting DC power from PV panels into AC power suitable for grid connection. Non-isolated solar inverters, in particular, have attracted considerable attention because of their compact size, lightweight design, cost-effectiveness, and high efficiency. However, the absence of transformer isolation in these systems introduces a parasitic capacitance between the PV array and the ground, leading to the generation of leakage currents. These leakage currents can cause grid current distortion, electromagnetic interference, and pose potential safety hazards to personnel. Therefore, addressing the leakage current issue in non-isolated solar inverters is of paramount importance for ensuring reliable and safe operation.
While single-phase non-isolated solar inverters have been extensively studied, their large-scale integration can lead to three-phase voltage imbalances in the grid. Consequently, standards such as VDE-AR-N 4105 limit the single-phase system capacity to below 4.6 kVA. In contrast, three-phase PV systems do not cause grid voltage imbalances and allow for higher grid-connected capacities, making them more suitable for medium- to large-scale applications. Traditional three-phase two-level solar inverters struggle to effectively suppress leakage currents, prompting research into improved modulation strategies and topological modifications. However, these solutions primarily focus on two-level topologies, which have limitations in terms of switching stress and output waveform quality. Three-level topologies, such as diode-clamped, flying capacitor, and cascaded configurations, offer advantages like reduced switching stress and better output waveforms but come with increased complexity, higher switch counts, and reliability concerns. For instance, diode-clamped topologies require 12 switches and 6 clamping diodes, while flying capacitor topologies need 12 switches and 3 flying capacitors, adding to system cost and control complexity. Moreover, these topologies often require intricate modulation strategies to coordinate switching states for leakage current suppression.
This paper investigates a three-phase six-switch three-level solar inverter topology that combines the benefits of reduced switch count, enhanced reliability, and effective leakage current attenuation. The proposed topology incorporates coupled inductors between the switches of each bridge arm to prevent shoot-through issues and improve system robustness. By analyzing the circuit operation and establishing a common-mode loop model, we explore the system’s common-mode behavior and propose a modulation strategy that achieves three-level output voltage while maintaining a constant common-mode voltage, thereby eliminating leakage currents. Additionally, we address issues related to inductor winding current discontinuity and provide solutions through improved modulation techniques. Experimental results on a digital control platform validate the effectiveness of the proposed approach, demonstrating significant leakage current reduction and high-quality output waveforms.
The three-phase six-switch three-level solar inverter topology is depicted in Figure 1 (conceptual representation). It consists of six IGBT switches (S1 to S6), six diodes (VD1 to VD6), and coupled inductors inserted between the switches of each bridge arm. The PV array is represented with a parasitic capacitance Cpv to ground, and icm denotes the leakage current. This configuration avoids bridge arm shoot-through, enhancing system reliability. The diodes provide freewheeling paths, and the system operates in four distinct states per phase, producing output voltage levels of Udc, Udc/2, and 0. The key innovation lies in the use of coupled inductors, which allow both switches in a bridge arm to be turned on or off simultaneously without causing short circuits, enabling the intermediate voltage level Udc/2.
To understand the operation, consider phase A: the inductor winding currents iw1 and iw2 flow in the same direction, and the magnetic circuit current im is influenced by the switching states. When both S1 and S2 are on, the inductor stores energy, and im increases; when both are off, the inductor releases energy, and im decreases; when one switch is on and the other off, the inductor windings are short-circuited, and im remains relatively constant. This behavior is summarized in Table 1.
| S1 | S2 | UAN | Inductor Winding State | im |
|---|---|---|---|---|
| 1 | 1 | Udc/2 | Energy storage | Increases |
| 0 | 0 | Udc/2 | Energy release | Decreases |
| 1 | 0 | Udc | Short-circuited | Constant |
| 0 | 1 | 0 | Short-circuited | Constant |
For tightly coupled inductors with coupling coefficient k = 1, the output current ia is equally divided between the two windings: iw1 = ia/2 + im/2 and iw2 = ia/2 – im/2. Only the leakage inductance of the coupled inductor appears in the output circuit, simplifying analysis. Decoupling the inductor yields an equivalent circuit where the common-mode voltage UCM is defined as:
$$ U_{CM} = \frac{U_{AN} + U_{BN} + U_{CN}}{3} $$
The common-mode circuit model, after simplification, shows that the leakage current icm is primarily driven by variations in UCM. Therefore, maintaining a constant UCM is crucial for leakage current suppression in this solar inverter topology.
To achieve proper operation and leakage current attenuation, we propose two modulation strategies. Modulation Strategy I uses two modulation signals m1 and m2, phase-shifted by 180°, compared with a single carrier wave to generate PWM signals for S1 and S2. This approach ensures that all switches operate at the carrier frequency throughout the modulation period. However, simulation results reveal that while three-level output voltage is achieved, the common-mode voltage fluctuates between Udc/3, Udc/2, and 2Udc/3, leading to significant leakage currents with peak values exceeding 861 mA, which violates the VDE-0126-1-1 standard limit of 300 mA. Additionally, inductor winding currents exhibit discontinuity due to diode voltage drops and other non-idealities, causing voltage spikes and reverse dips in the output, as shown in Figure 8 (simulated waveforms). To address this, we introduce a turn-off delay of 1 μs, which eliminates current discontinuity and improves waveform quality, but leakage currents remain above the standard limit.
Modulation Strategy II is designed to maintain a constant common-mode voltage at Udc/2, thereby suppressing leakage currents. This strategy involves carrier comparison and logical transformations to generate switch signals. A frequency-divided signal P, at twice the carrier frequency, is used to balance energy storage and release in the inductor windings over one carrier period. The Boolean logic functions for switches S1 to S6 are:
$$ \begin{align*}
S1 &= XZ + XP + ZP \\
S2 &= XZ + ZP + XP \\
S3 &= YX + YP + XP \\
S4 &= YX + XP + YP \\
S5 &= ZY + ZP + YP \\
S6 &= ZY + YP + ZP
\end{align*} $$
where X, Y, Z are initial PWM signals from modulation wave-carrier comparisons, and P is the frequency-divided signal. With a 50% duty cycle for P, simulation results show reduced common-mode voltage variations and leakage currents, but inductor winding current discontinuity persists, leading to voltage spikes. By increasing the duty cycle of P to 51%, the winding currents become continuous, and the common-mode voltage stabilizes at Udc/2. This results in effective leakage current suppression, with peak values reduced to below 96 mA, meeting the VDE standard. The output current THD is 1.10%, indicating high waveform quality.
We conducted experiments on a digital control platform with TMS320F28335 DSP and XC3S400 FPGA to validate the proposed solar inverter design. Parameters included: DC bus voltage Udc = 250 V, switching frequency 10 kHz, filter inductance 2.5 mH, coupled inductance 2.14 mH with coupling coefficient 0.99, and parasitic capacitance 200 nF. For Modulation Strategy I without turn-off delay, phase voltages showed three-level output, but parasitic capacitor voltage fluctuated, and winding currents were discontinuous, causing voltage irregularities. Adding a turn-off delay improved current continuity, but leakage currents peaked at 324 mA, still above the standard. With Modulation Strategy II and a 51% duty cycle for P, winding currents became continuous, parasitic capacitor voltage remained constant, and leakage currents were suppressed to 96 mA. Three-phase output currents exhibited low harmonic distortion, confirming the effectiveness of the proposed modulation for this solar inverter.
The performance of the solar inverter under different modulation strategies is summarized in Table 2, highlighting key metrics such as common-mode voltage behavior, leakage current magnitude, and output waveform quality.
| Modulation Strategy | Common-Mode Voltage | Leakage Current Peak | Inductor Winding Current | Output Voltage Quality | Compliance with VDE Standard |
|---|---|---|---|---|---|
| Strategy I (no delay) | High fluctuations | >861 mA | Discontinuous | Poor due to spikes | No |
| Strategy I (with delay) | Reduced fluctuations | 324 mA | Continuous | Improved | No |
| Strategy II (50% duty cycle) | Moderate fluctuations | ~200 mA (simulated) | Discontinuous | Moderate | No |
| Strategy II (51% duty cycle) | Constant at Udc/2 | 96 mA | Continuous | Good, THD=1.10% | Yes |
From an analytical perspective, the common-mode voltage dynamics can be modeled using differential equations. The leakage current icm is given by:
$$ i_{cm} = C_{pv} \frac{dU_{CM}}{dt} $$
where Cpv is the parasitic capacitance. By ensuring dUCM/dt = 0, leakage currents are minimized. In Strategy II, the switching states are selected to satisfy this condition. For instance, during a switching period, the average common-mode voltage is maintained at Udc/2 through careful timing of switch states. The mathematical formulation for the output phase voltages in terms of switch states is:
$$ \begin{align*}
U_{AN} &= \frac{U_{dc}}{2} (S1 \cdot S2 + \overline{S1} \cdot \overline{S2}) + U_{dc} \cdot S1 \cdot \overline{S2} \\
U_{BN} &= \frac{U_{dc}}{2} (S3 \cdot S4 + \overline{S3} \cdot \overline{S4}) + U_{dc} \cdot S3 \cdot \overline{S4} \\
U_{CN} &= \frac{U_{dc}}{2} (S5 \cdot S6 + \overline{S5} \cdot \overline{S6}) + U_{dc} \cdot S5 \cdot \overline{S6}
\end{align*} $$
where overline denotes logical NOT. Substituting into the common-mode voltage equation yields:
$$ U_{CM} = \frac{U_{dc}}{6} \left[ (S1 \cdot S2 + \overline{S1} \cdot \overline{S2}) + (S3 \cdot S4 + \overline{S3} \cdot \overline{S4}) + (S5 \cdot S6 + \overline{S5} \cdot \overline{S6}) \right] + \frac{U_{dc}}{3} \left( S1 \cdot \overline{S2} + S3 \cdot \overline{S4} + S5 \cdot \overline{S6} \right) $$
By designing modulation sequences such that the sum of the terms in brackets equals 3 and the sum of the latter terms equals 0 on average, UCM = Udc/2 is achieved. This is realized through the Boolean functions in Strategy II.
The inductor design is critical for this solar inverter. The coupled inductor must have high coupling coefficient to minimize leakage inductance, which affects output current ripple. The magnetic circuit current im can be expressed as:
$$ \frac{d i_m}{dt} = \frac{U_{dc}}{2L} (S1 \cdot S2 – \overline{S1} \cdot \overline{S2}) $$
where L is the inductance of each winding. Energy balance requires that over a switching period, the net change in im is zero to prevent saturation. The frequency-divided signal P in Strategy II ensures this balance by adjusting the duty cycle, as demonstrated experimentally.
In terms of grid integration, the proposed solar inverter must comply with power quality standards. The output current harmonics are influenced by the modulation strategy and filter design. The filter inductance Lf and the equivalent series resistance (ESR) determine the current ripple Δi:
$$ \Delta i = \frac{U_{dc}}{8 L_f f_{sw}} $$
where fsw is the switching frequency. For our parameters, Δi is within acceptable limits, and the low THD confirms good performance.
The solar inverter’s efficiency is another key consideration. The reduced switch count (six switches compared to twelve in traditional three-level topologies) lowers conduction and switching losses. The total power loss Ploss can be estimated as:
$$ P_{loss} = P_{cond} + P_{sw} + P_{core} $$
where Pcond is conduction loss in switches and diodes, Psw is switching loss, and Pcore is core loss in the inductors. Using datasheet values for IGBTs and diodes, simulations show efficiency above 98% under rated conditions, making this solar inverter competitive for commercial applications.
Future work could explore adaptive modulation techniques that adjust the duty cycle of signal P based on load variations to maintain current continuity under all operating conditions. Additionally, integrating maximum power point tracking (MPPT) algorithms and grid synchronization functions into the control platform would enhance the solar inverter’s functionality. The use of wide-bandgap devices like SiC or GaN could further improve efficiency and switching frequency, allowing for smaller passive components.
In conclusion, this paper presents a comprehensive study on leakage current suppression in a three-phase six-switch three-level solar inverter. Through theoretical analysis and experimental validation, we demonstrate that Modulation Strategy II, with an adjusted duty cycle for the frequency-divided signal, effectively maintains a constant common-mode voltage and eliminates leakage currents while producing high-quality three-level output voltages. The proposed solar inverter topology offers a balance between performance, reliability, and cost, making it a promising solution for medium- to large-scale PV systems. As the demand for efficient and safe solar inverters continues to grow, such innovations will play a vital role in advancing renewable energy integration.