In the context of global energy transition towards decarbonization, large-scale photovoltaic (PV) power generation has become a cornerstone of modern power systems. Particularly in regions with abundant solar resources, such as deserts and arid areas, massive PV bases are constructed to harness renewable energy. These bases are often integrated into the grid via long-distance transmission systems, which predominantly employ power electronic interfaces like voltage source converter-based high-voltage direct current (VSC-HVDC) technology. However, this evolution introduces new challenges in power quality, especially concerning the dynamic behavior of solar inverters during and after grid disturbances. One emerging issue is the DC-side voltage dip of solar inverters following fault clearance in the AC system—a phenomenon driven by control responses rather than direct faults. This article delves into the mechanisms behind this voltage dip and proposes an effective mitigation strategy, emphasizing the role of solar inverters in maintaining system stability.
The proliferation of solar inverters in power systems has transformed grid dynamics, as these devices exhibit fast control responses but low inherent inertia. In large-scale PV transmission systems, where solar inverters constitute a high proportion of generation sources, their interaction with the grid during faults can lead to unintended consequences. Specifically, after an AC fault is cleared, solar inverters may experience a significant drop in DC-link voltage, which can persist and affect the overall system performance. This DC-side voltage dip is not merely a transient issue; it can trigger cascading failures, such as tripping of solar inverters due to undervoltage protection, thereby jeopardizing grid reliability. Understanding and addressing this problem is crucial for the secure operation of future power networks dominated by renewable energy sources.
To begin, let’s explore the fundamental principles governing solar inverters in PV systems. A typical grid-connected PV unit consists of a PV array, a DC-link capacitor, and a solar inverter that converts DC power to AC power for grid injection. The power balance within this unit is pivotal to voltage stability. The DC-link voltage $U_{dc}$ dynamics can be described by the equation:
$$ C U_{dc} \frac{dU_{dc}}{dt} = P_{pv} – P_g $$
where $C$ is the capacitance of the DC-link capacitor, $P_{pv}$ is the power generated by the PV array, and $P_g$ is the power output from the solar inverter to the grid. Under normal conditions, $P_{pv} \approx P_g$, leading to a stable $U_{dc}$. However, during disturbances, imbalances arise. The output power of a solar inverter is controlled via a dq-frame current regulator, with the active power $P_g$ given by:
$$ P_g = \frac{3}{2} (u_d i_d + u_q i_q) = \frac{3}{2} U_g i_d $$
assuming grid voltage orientation where $u_d = U_g$ (grid voltage magnitude) and $u_q = 0$. Here, $i_d$ and $i_q$ are the d-axis and q-axis current components, respectively. Solar inverters typically operate with maximum power point tracking (MPPT) to optimize $P_{pv}$, but during faults, control modes may shift, such as entering low-voltage ride-through (LVRT) to support grid voltage with reactive power injection. This shift can disrupt the active power balance, leading to DC-side voltage deviations.
The DC-side voltage dip phenomenon is intricately linked to the operational states of solar inverters. Based on the relative position of the PV array operating point on its P-V curve and the control status of the solar inverter, we can categorize system conditions into four distinct scenarios, as summarized in Table 1. This classification helps in understanding the evolution of voltage dips. In Scenario 1, the solar inverter operates normally with the PV array to the right of the maximum power point (MPP), and no LVRT is activated. Scenario 2 is similar but with the PV array to the left of MPP. In Scenario 3, LVRT is active, and the PV array is to the right of MPP, while in Scenario 4, LVRT is active with the PV array to the left of MPP. The transition between these scenarios, especially from Scenario 1 to Scenario 2 and then to Scenario 4, is critical for DC-side voltage dip occurrence. When a distant fault occurs in the AC system, solar inverters may not immediately detect it via AC voltage sag, leading to prolonged operation in Scenario 1. After fault clearance, if the solar inverter rapidly restores active power output, $P_g$ exceeds $P_{pv}$, causing $U_{dc}$ to fall. This pushes the PV array leftward of MPP, reducing $P_{pv}$ further and exacerbating the imbalance. Eventually, if $U_{dc}$ drops enough to trigger LVRT (due to AC voltage dip propagation), the system enters Scenario 4, where the solar inverter prioritizes reactive power, leaving active power uncontrolled and $U_{dc}$ depressed indefinitely.
| Scenario | PV Array Operating Point | Solar Inverter Control State | DC-Link Voltage Tendency |
|---|---|---|---|
| Scenario 1 | Right of MPP | Normal (No LVRT) | Stable or Slightly Rising |
| Scenario 2 | Left of MPP | Normal (No LVRT) | Falling |
| Scenario 3 | Right of MPP | LVRT Active | Moderately Rising |
| Scenario 4 | Left of MPP | LVRT Active | Severely Falling |
To mitigate this issue, we propose a strategy comprising two main components: enhanced fault detection and active power output limitation for solar inverters. The fault detection part addresses the challenge for remote solar inverters that cannot quickly sense AC faults. Since faults cause a blockage in power output from solar inverters, leading to DC-link overvoltage, we introduce $U_{dc}$ as an additional detection criterion. A threshold $U_{dc,over}$ (e.g., 1.1 per unit) is set; when $U_{dc}$ exceeds this, a fault is deemed detected, and the mitigation strategy is activated. This allows solar inverters to respond promptly even to distant faults.
The active power output limitation part aims to prevent rapid restoration of active current $i_d$ after fault clearance, thereby maintaining power balance. Upon fault detection, the solar inverter switches from normal voltage control to a constant active current control mode. The reference active current $i_{d,ref}$ is set to a low value, such as zero, and then ramped up gradually at a controlled slope $k$ until it reaches the pre-fault value $i_{d,refl}$. This approach limits the rate of increase in $P_g$, allowing $P_{pv}$ to catch up and avoiding a sharp decline in $U_{dc}$. The ramp-up slope $k$ must be carefully chosen to match the power restoration capability of the VSC-HVDC link, preventing overvoltage at the converter station due to power surplus. The active current recovery profile can be expressed as:
$$ i_{d,ref}(t) = \begin{cases}
0 & \text{for } t \leq t_0 \\
\min(i_{d,refl}, k (t – t_0)) & \text{for } t > t_0
\end{cases} $$
where $t_0$ is the time when fault detection occurs. This strategy ensures that solar inverters do not transition into Scenario 4, effectively suppressing DC-side voltage dips.
Simulation studies are conducted to validate the proposed mitigation strategy for solar inverters. A model of a large-scale PV transmission system is built in PSCAD/EMTDC, comprising three PV bases (PV1, PV2, PV3) with capacities of 3000-4000 MW each, connected via AC lines to a VSC-HVDC station. The parameters of the AC lines are detailed in Table 2, which includes length, per-unit resistance, reactance, and capacitance. These parameters influence the dynamic response of solar inverters during faults. A three-phase short-circuit fault is applied at the converter station AC bus at t = 10.5 s, lasting 100 ms. Without mitigation, solar inverters at remote PV bases (PV1 and PV2) exhibit sustained DC-side voltage dips below 0.9 p.u. for about 0.4 s after fault clearance, while the nearby PV3 does not, confirming the mechanism. With the mitigation strategy enabled, $U_{dc,over}$ is set to 1.1 p.u., and the active current ramp-up slope $k$ is selected as 2.0 p.u./s based on studies to avoid overvoltage at the VSC-HVDC station. The results show that DC-side voltage dips are effectively prevented, with $U_{dc}$ recovering smoothly.
| Line ID | Length (km) | Resistance (p.u./m) | Reactance (p.u./m) | Capacitance (p.u./m) | Base Voltage (kV) | Base Power (MVA) |
|---|---|---|---|---|---|---|
| 1 | 27 | 5.470e-09 | 9.700e-08 | 1.167e-05 | 525 | 100 |
| 2 | 58 | 5.130e-09 | 9.590e-08 | 1.186e-05 | 525 | 100 |
| 3 | 39 | 5.130e-09 | 9.590e-08 | 1.186e-05 | 525 | 100 |
| 4 | 235 | 5.990e-09 | 7.580e-08 | 1.470e-05 | 525 | 100 |
The choice of $k$ is critical for the performance of solar inverters. To determine the optimal slope, simulations are run with varying $k$ from 1.0 to 7.0 p.u./s. The results, summarized in Table 3, indicate that for $k \leq 2.0$ p.u./s, the VSC-HVDC station bus voltage remains below 1.1 p.u., avoiding overvoltage. For $k \geq 3.0$ p.u./s, overvoltage occurs due to power mismatch. Hence, $k = 2.0$ p.u./s is chosen as a balance between rapid power restoration and system stability. This underscores the importance of coordinating solar inverters with the broader grid infrastructure.
| Slope $k$ (p.u./s) | Max VSC-HVDC Bus Voltage (p.u.) | Overvoltage Occurrence | DC-Side Voltage Dip in Solar Inverters |
|---|---|---|---|
| 1.0 | 1.08 | No | Suppressed |
| 2.0 | 1.09 | No | Suppressed |
| 3.0 | 1.12 | Yes | Partially Suppressed |
| 4.0 | 1.15 | Yes | Not Suppressed |
| 5.0 | 1.18 | Yes | Not Suppressed |
| 6.0 | 1.20 | Yes | Not Suppressed |
| 7.0 | 1.22 | Yes | Not Suppressed |
Further analysis involves different fault types, such as two-phase-to-ground faults, to test the robustness of the mitigation strategy for solar inverters. Simulation results confirm that the strategy works effectively across various fault scenarios, preventing DC-side voltage dips in all remote solar inverters. The key is the early detection via DC overvoltage and the controlled active current recovery. This highlights the adaptability of solar inverters when equipped with advanced control algorithms.
In conclusion, the DC-side voltage dip in solar inverters within large-scale PV transmission systems is a nascent power quality issue stemming from control responses post-fault clearance. The mechanism involves a sequence of operational scenario transitions, ultimately leading to Scenario 4 where voltage remains depressed. Our proposed mitigation strategy addresses this by enhancing fault detection through DC-link voltage monitoring and limiting active power output via constant active current control with a tailored ramp-up slope. Simulation results validate that this strategy effectively suppresses voltage dips while maintaining grid stability. Future work could focus on real-time implementation and optimization of parameters for diverse system configurations. As solar inverters become increasingly prevalent, such strategies will be vital for ensuring the reliability and resilience of renewable-rich power grids.
The integration of solar inverters into power systems necessitates continuous innovation in control techniques. By understanding the dynamics of solar inverters during faults, we can develop more robust solutions that enhance grid compatibility. The proposed strategy not only mitigates DC-side voltage dips but also contributes to the overall stability of VSC-HVDC-based transmission networks. As the energy landscape evolves, the role of solar inverters will expand, requiring ongoing research into their behavior and control. This article provides a foundational approach that can be adapted and refined for future systems, ensuring that solar power remains a reliable and sustainable energy source.