The pursuit of clean and sustainable energy has placed solar power at the forefront of technological innovation. Central to harnessing this energy is the photovoltaic (PV) system, where the solar inverter performs the critical function of converting direct current (DC) from PV panels into grid-compliant alternating current (AC). The efficiency, cost, and reliability of these solar inverters are paramount for the economic viability of solar installations. Consequently, significant research is dedicated to advancing inverter topologies and control methodologies.
Modern grid-connected solar inverters are categorized based on the use of transformers: with high-frequency transformers, with low-frequency (line-frequency) transformers, and transformerless. Transformerless solar inverters have gained substantial attention due to their higher efficiency, reduced weight, smaller size, and lower cost compared to their transformer-isolated counterparts. The absence of a transformer, however, introduces a significant technical challenge: the generation of leakage currents. This common-mode (CM) current flows through the parasitic capacitance between the PV array and ground, which can be substantial and variable with environmental conditions. These leakage currents can lead to safety hazards, electromagnetic interference (EMI), increased grid current distortion, and reduced system efficiency. Therefore, the design of transformerless solar inverters must inherently address and suppress this leakage current.
Analysis of Leakage Current in Conventional Topologies
The root cause of leakage current in transformerless solar inverters is the variation of the common-mode voltage (\(V_{cm}\)). The common-mode voltage for a circuit can be defined as the average potential of the output terminals with respect to the ground. A fluctuating \(V_{cm}\) imposes a changing voltage across the PV parasitic capacitance (\(C_{pv}\)), driving the leakage current (\(i_{leak}\)). This relationship is governed by the fundamental equation:
$$ i_{leak} = C_{pv} \frac{dV_{cm}}{dt} $$
This indicates that the magnitude of the leakage current is directly proportional to the size of the parasitic capacitance and the rate of change of the common-mode voltage. To achieve low leakage currents, the topology must ensure that \(V_{cm}\) remains constant or varies at a very low frequency (e.g., grid frequency).
Classical inverter topologies exhibit different leakage characteristics:
- Full-Bridge Inverter with Unipolar Modulation: While offering good output waveform quality, this configuration generates a high-frequency pulsating \(V_{cm}\), resulting in substantial high-frequency leakage currents.
- Full-Bridge Inverter with Bipolar Modulation: Here, the \(V_{cm}\) is clamped to half of the DC bus voltage (\(U_{dc}/2\)). Although constant in principle, practical switching dead times can cause minor fluctuations.
- Half-Bridge Inverter: The midpoint of the input DC-link capacitors is typically grounded, clamping the parasitic capacitance voltage to \(U_{dc}/2\). This effectively minimizes leakage current but requires a high DC input voltage and has limited utilization of the switching devices.
The following table summarizes the leakage current behavior of these basic topologies:
| Topology & Modulation | Common-Mode Voltage (\(V_{cm}\)) Characteristic | Leakage Current Risk |
|---|---|---|
| Full-Bridge, Unipolar PWM | High-frequency switching pulses | Very High |
| Full-Bridge, Bipolar PWM | Constant at \(U_{dc}/2\) (ideally) | Low (with careful design) |
| Half-Bridge | Clamped to \(U_{dc}/2\) via midpoint | Very Low |
The Dual Buck Inverter and its Evolution to a Three-Level Topology
A promising alternative to bridge-based structures is the Dual Buck Inverter. Its fundamental principle is semi-cycle operation, employing two independent Buck converter circuits. During the positive half-cycle of the output current, one Buck circuit (comprising a switch, diode, and inductor) is active. During the negative half-cycle, the second Buck circuit takes over. This inherent structure eliminates the possibility of shoot-through faults, a critical reliability advantage. Furthermore, the body diodes of the main switches never conduct, reducing reverse recovery losses. However, the classic dual Buck solar inverter has a key drawback: each main switch must block the full DC bus voltage (\(U_{dc}\)), and the output voltage remains a two-level waveform with significant harmonic content.
To overcome these limitations, an advanced three-level Dual Buck solar inverter topology has been developed. This novel structure replaces each main switch in the traditional dual Buck circuit with a composite switch cell consisting of two active switches and a diode. This modification fundamentally alters the output capability, allowing the generation of three voltage levels at the bridge arms: \(+U_{dc}\), \(0\), and \(-U_{dc}\). The most significant benefit of this architecture for transformerless solar inverters is its innate leakage current suppression. By strategically connecting the midpoint of the input DC-link capacitors to the circuit, the common-mode voltage is effectively clamped. The parasitic capacitance of the PV array sees a nearly constant voltage, drastically reducing \(di_{leak}/dt\) as per the fundamental equation.
The operation of this three-level dual Buck solar inverter can be detailed through its switching modes. For the positive output current half-cycle (Buck1 active), and the negative half-cycle (Buck2 active), the switch states and resulting voltages are systematically defined. The table below outlines the primary operating modes:
| Current Polarity | Mode | Key Switches ON | Bridge Output (u) | Inductor Current (iL) |
|---|---|---|---|---|
| iL > 0 (Buck1 Active) | 1 (Powering) | S1, S2 | +Udc | Increases |
| 2 (Freewheeling) | S3 (via D3) | 0 | Decreases | |
| iL < 0 (Buck2 Active) | 1 (Powering) | S4, S3 | -Udc | Decreases (negatively) |
| 2 (Freewheeling) | S2 (via D4) | 0 | Increases (towards zero) |
This switching sequence ensures that at no point does a high-frequency voltage swing appear across the parasitic capacitance to ground, fulfilling the core requirement for leakage-free operation in transformerless solar inverters.
Advanced Control Strategy for Three-Level Dual Buck Solar Inverters
A sophisticated control strategy is essential to leverage the full potential of the three-level dual Buck solar inverter. The control objectives are multi-faceted: (1) track the maximum power point (MPPT) of the PV array, (2) regulate the output current to be sinusoidal and in phase with the grid voltage, and (3) maintain voltage balance across the two input DC-link capacitors (\(C_1\) and \(C_2\)). Imbalance in these capacitor voltages can distort output waveforms, increase stress on components, and impair the leakage current suppression feature.
A composite control strategy employing multiple feedback loops is proposed. The system utilizes a voltage balance control loop, an inner current control loop, and an outer current reference generation loop. The workflow is as follows: The PV array voltage and current are sampled for MPPT calculation (e.g., using Perturb and Observe algorithm), generating the amplitude reference (\(I_{mpp}\)) for the grid current. Simultaneously, the voltages of capacitors \(C_1\) (\(U_{C1}\)) and \(C_2\) (\(U_{C2}\)) are measured. The balance controller processes the error \(\Delta U = U_{C1} – U_{C2}\) (or \(U_{C1} – U_{dc}/2\)). The output of this controller is a corrective current offset (\(\Delta i\)).
The final current reference for the inner loop (\(i_{ref}\)) is constructed as:
$$ i_{ref} = i_g^* – \Delta i $$
$$ \text{where } i_g^* = I_{mpp} \cdot \sin(\omega t) $$
This reference is compared with the measured inverter output current (\(i_L\)). The error is processed by a high-bandwidth proportional-integral (PI) or proportional-resonant (PR) current controller. The controller’s output is a modulating signal which is compared with a triangular carrier wave to generate the Sinusoidal Pulse Width Modulation (SPWM) signals for the switches S1-S4. The inner current loop’s dynamic response ensures high-quality grid current injection.
The rationale for the capacitor voltage imbalance can be analyzed from the capacitor currents. Assuming the grid current is sinusoidal, \(i_L = I_L \sin(\omega t + \phi)\), the currents through \(C_1\) and \(C_2\) (\(i_{C1}\), \(i_{C2}\)) are derived from the circuit’s switching average model. Their average values over a switching cycle, but containing low-frequency (grid frequency) components, lead to voltage deviations. The steady-state voltage imbalance \(\Delta U\) can be expressed as:
$$ \Delta U = U_{C1} – U_{C2} = \frac{2 I_L}{\omega (C_1 + C_2)} $$
where \(\omega\) is the grid angular frequency. This formula highlights that the imbalance is inversely proportional to the total capacitance \((C_1 + C_2)\). The balance control loop actively compensates for this inherent tendency, ensuring \(U_{C1} \approx U_{C2} \approx U_{dc}/2\).
Simulation Verification and Performance Analysis
To validate the proposed three-level dual Buck solar inverter topology and its composite control strategy, a detailed simulation model is constructed with the following parameters:
- DC Input Voltage (\(U_{dc}\)): 720 V
- Input Capacitors (\(C_1, C_2\)): 1100 µF each
- Output Filter Inductors (\(L_1, L_2\)): 750 µH each
- Output: 220 V (RMS), 50 Hz, 1 kW
- Switching Frequency: 20 kHz
The simulation results demonstrate several key performance metrics. The grid voltage (\(u_g\)) and the inverter output current (\(i_L\)) are perfectly sinusoidal and in phase, confirming unity power factor operation and accurate current tracking. The voltages across the input capacitors, \(U_{C1}\) and \(U_{C2}\), are maintained precisely around 360 V (half of \(U_{dc}\)), with only minimal ripple, proving the effectiveness of the voltage balance control loop. The gate drive signals for the switches (V1-V4) show the complementary three-level modulation pattern as described in the operating modes.
Most importantly, the common-mode voltage (\(V_{cm}\)) measured in the simulation remains virtually constant at \(U_{dc}/2\), with no high-frequency components. According to the fundamental leakage current equation \(i_{leak} = C_{pv} \frac{dV_{cm}}{dt}\), this results in a leakage current magnitude that is negligible, limited only by the very low \(dV_{cm}/dt\) at the grid frequency. This conclusively verifies the topology’s superior performance in mitigating ground leakage currents, a critical achievement for transformerless solar inverters.
Conclusion and Future Perspectives
The advancement of transformerless solar inverters is crucial for enhancing the efficiency and reducing the cost of photovoltaic energy conversion. This article has detailed the inherent challenge of leakage current in such systems and traced the evolution from conventional bridge topologies to the innovative three-level dual Buck solar inverter. By employing a composite switch cell structure, this topology achieves three-level output, reducing harmonic distortion and, more importantly, clamping the common-mode voltage to suppress leakage current at its source.
The accompanying composite control strategy, integrating maximum power point tracking, capacitor voltage balancing, and high-performance current regulation, provides a robust solution for stable and efficient grid integration. Simulation studies confirm the theoretical analysis, demonstrating excellent output waveform quality, stable capacitor voltage balance, and most significantly, effective elimination of high-frequency leakage currents.
Future research directions for solar inverters based on this topology may include: extending the concept to three-phase systems for higher power applications; integrating advanced wide-bandgap semiconductor devices (e.g., SiC MOSFETs, GaN HEMTs) to push efficiency and switching frequency even higher; developing model predictive control (MPC) strategies for improved dynamic response; and exploring seamless integration with battery energy storage systems within a unified power conversion platform. The continuous refinement of topologies like the three-level dual Buck inverter will undoubtedly play a pivotal role in the next generation of high-efficiency, reliable, and safe solar inverters.