In recent years, the rapid integration of renewable energy sources and energy storage systems has led to power grids exhibiting characteristics of weak or even extremely weak grids. The interaction between grid-connected inverters and such weak grids can induce system instability, severely constraining the safe and stable operation of new energy power systems. The phase-locked loop (PLL) is a critical component that synchronizes the inverter with the grid by detecting voltage information at the point of common coupling (PCC). However, variations in grid impedance can adversely affect PLL stability, thereby challenging the stability of the grid-connected system. Particularly, as grid impedance increases, harmonic amplification becomes more pronounced, exacerbating the risk of system instability triggered by the PLL. Therefore, investigating the impact of PLL on system stability and exploring methods to enhance phase-locking accuracy under large grid impedance and distorted grid voltage conditions is essential for ensuring grid security and stability.
Impedance-based analysis methods have been widely applied to address such issues. Control strategies for grid-connected inverters based on PLL have garnered significant attention, primarily including inverter impedance optimization design and inverter impedance reshaping control. The impedance optimization strategy improves system stability by tuning PLL parameters. However, due to the inherent resonant frequency characteristics of LCL filters, this optimization often focuses on adjusting the PLL bandwidth to improve the output impedance characteristics of the inverter. This approach frequently requires a trade-off between dynamic performance and steady-state performance, such as reducing PLL bandwidth to enhance stability, which consequently limits system response speed. Consequently, research focus has shifted toward reshaping the impedance of grid-connected inverters by improving the PLL structure. To mitigate AC components generated by the PLL under varying grid conditions that cannot be compensated by PI controllers, researchers have proposed feedback control architectures based on PI-controlled synchronous reference frame PLL (SRF-PLL). These architectures incorporate low-pass filters, notch filters, integrators, etc., at different stages to pre-filter non-ideal grid information, reducing output fluctuations and enhancing steady-state filtering capability. Examples include the moving average filter PLL (MAF-PLL), multiple-complex coefficient-filter-based PLL (MCCF-PLL), second-order generalized integrator PLL (SOGI-PLL), adaptive notch filter PLL (ANF-PLL), and their improved versions, which have achieved progress in enhancing dynamic performance or stability.
For single-phase applications, PLLs constructed based on the second-order generalized integrator (SOGI) can filter high-frequency voltage components without delay. However, during grid frequency fluctuations, unequal amplitudes of orthogonal output signals generate significant double-frequency harmonics and offset errors. To address this, a multi-cascaded SOGI method has been proposed to effectively detect harmonic components and separate fundamental positive-sequence components, but its structure is complex. Adding a low-pass filter to the traditional SOGI-OSG structure can eliminate DC components, but this reduces system bandwidth, affects dynamic response speed, and complicates filter parameter design. The fixed-frequency SOGI (FFSOGI) provides accurate synchronization performance under frequency drift, but its advantages are limited to specific environments. Although progress has been made in anti-interference capability and system stability for SRF-PLL based on PI controllers, challenges and limitations remain. Therefore, further research to explore more efficient and stable PLL structures and control methods is still a key direction.
Linear active disturbance rejection control (LADRC) is a control method that addresses coupling, uncertainties, and disturbances in systems. It treats coupling, uncertainties, and internal/external disturbances uniformly as “unknown disturbances” and employs a linear extended state observer (LESO) as a core component for estimation and compensation, thereby improving dynamic stability and anti-interference capability of control systems. Replacing traditional PI controllers with LADRC controllers has shown better control performance. Substituting the PI controller in SRF-PLL with LADRC can eliminate harmonic interference and mitigate the impact of system parameter variations caused by voltage imbalance. However, the LESO behaves like a low-pass filter, only estimating disturbances composed of low-frequency harmonics, resulting in suboptimal phase-locking accuracy. Using a nonlinear extended state observer improves LADRC-PLL performance but introduces computational complexity and analytical difficulties. Employing a generalized integrator to transform the LESO can further enhance harmonic suppression in LADRC-PLL, but due to harmonic diversity, multiple parallel generalized integrators are needed, complicating parameter tuning.
To address system instability, it is necessary to improve the dynamic response and steady-state filtering capability of the PLL. In this paper, we propose a novel PLL structure that combines FFSOGI with LADRC-PLL. This structure aims to reshape the phase characteristics of the equivalent output impedance of the grid-connected inverter system, thereby achieving stable frequency and phase synchronization control. By reshaping the inverter output impedance phase, the phase-frequency characteristics of the equivalent output impedance are enhanced within a feasible phase angle range, improving the inverter system’s adaptability to grid impedance. Simulation and experimental results demonstrate that the proposed novel PLL structure exhibits good transient response speed and steady-state filtering capability, enabling accurate phase-locking under weak grid conditions while reshaping the inverter system output impedance, effectively broadening the system’s adaptability range to grid impedance.
The topology and control block diagram of a single-phase grid-connected inverter are depicted. The inverter employs an LCL filter, with $L_1$, $L_2$, and $C$ representing the inverter-side inductance, grid-side inductance, and filter capacitance, respectively. $U_{dc}$ is the DC voltage, $u_g$ is the grid voltage, $i_c$ is the capacitor current, $i_2$ is the grid current, $u_{pcc}$ is the voltage at PCC, $L_g$ is the grid impedance assumed purely inductive, $I_2$ is the reference grid current amplitude, $i_{ref}$ is the grid current reference, $k_{PWM}$ is the equivalent modulation gain, $k_d$ is the active damping coefficient, $\theta$ is the PLL output phase angle, $k_{p-PLL}$ and $k_{i-PLL}$ are the proportional and integral coefficients of the PI controller in the PLL, and $G_c(s)$ is the current controller transfer function using quasi-proportional resonant (QPR) control. The traditional PLL control structure has a transfer function $G_{PLL}(s)$ given by:
$$G_{PLL}(s) = \frac{1}{U_m} \left( k_{p-PLL} + \frac{k_{i-PLL}}{s} \right)$$
where $U_m$ is the amplitude of $u_{pcc}$.
To analyze the output impedance characteristics of the grid-connected inverter system under weak grid conditions, the system control structure is equivalently transformed. The output current $i_2(s)$ can be expressed as:
$$i_2(s) = \frac{1}{Z_{out-PLL}(s) + Z_g(s)} u_g(s)$$
where $Z_{out-PLL}(s)$ is the system output impedance considering PLL, and $Z_g(s) = L_g s$ is the grid impedance. Based on impedance stability criterion, the system is stable if the phase margin (PM) is greater than 0°, i.e., the phase of the inverter output impedance at the crossover frequency must be greater than -90°. The equivalent impedance model is shown, where $Z_{PLL}$ represents the negative impedance introduced by the PLL, and $Z_{out}$ is the output impedance without PLL. The relationship is:
$$Z_{out-PLL}(s) = Z_{out}(s) – Z_{PLL}(s)$$
Analyzing the Bode plots of $Z_{out-PLL}$ and $Z_{out}$, it is observed that in the frequency range of 50 to 1000 Hz, the phase of $Z_{PLL}$ is less than that of $Z_{out}$, acting as a negative impedance. Compared to $Z_{out}$, the phase of $Z_{out-PLL}$ at the crossover frequency decreases significantly, reducing system stability margin or even causing instability as grid impedance varies. To mitigate the impact of negative impedance $Z_{PLL}$, the phase-frequency characteristic curve of the inverter equivalent output impedance needs to be extended to lower frequencies above -90°, requiring improvements in PLL structure to enhance stability margin in the crossover frequency range.
We propose a novel PLL structure combining LADRC-PLL and FFSOGI to address these issues. The control structure integrates FFSOGI for impedance phase reshaping and LADRC for disturbance rejection. The novel PLL structure is designed to improve dynamic performance and anti-interference capability. The FFSOGI-LADRC-PLL structure includes an FFSOGI block that generates orthogonal signals $u_\alpha$ and $u_\beta$ from $u_{pcc}$, ensuring equal amplitude and orthogonality even under frequency variations. The LADRC replaces the traditional PI controller, with its linear extended state observer (LESO) estimating and compensating disturbances. A phase compensation block is added to correct base-frequency phase deviations.
The LADRC controller consists of three parts: linear extended state observer (LESO), disturbance compensator (DC), and linear state error feedback (LSEF). The control law is given by:
$$u = k_{P1} (u_q^* – Z_1) – \frac{Z_2}{b_0}$$
where $u_q^*$ is the reference q-axis component (set to zero for PLL), $k_{P1}$ is the LSEF proportional gain, $Z_1$ and $Z_2$ are LESO outputs, and $b_0$ is the control gain. The LESO is designed with observer bandwidth $\omega_{01}$, and the controller bandwidth $\omega_{c1}$. Typically, $\omega_{01} = 4\omega_{c1}$ for a balance between estimation speed and noise sensitivity. The transfer function of LADRC can be derived as:
$$G_{LADRC}(s) = \frac{k_{P1} b_0}{s^2 + \beta_1 s + \beta_2}$$
where $\beta_1$ and $\beta_2$ are observer gains related to $\omega_{01}$.
The FFSOGI block ensures accurate orthogonal signal generation under fixed nominal frequency $\omega_1 = 2\pi \times 50$ rad/s. The transfer function for FFSOGI is:
$$G_{FFSOGI}(s) = \frac{k \omega_1 s}{s^2 + k \omega_1 s + \omega_1^2}$$
where $k$ is the gain coefficient, typically set to 1.63 for fast settling. The estimated phase angle $\hat{\theta}$ is obtained with a small phase correction $\delta$ due to frequency deviation $\Delta \omega$:
$$\delta \approx \frac{\Delta \omega}{\omega_1}, \quad \hat{\theta} = \theta + \delta$$
To compensate for base-frequency phase deviation, a lead compensator is added with transfer function:
$$G_{pc}(s) = \frac{\tau_1 s + 1}{\tau_2 s + 1}$$
where $\tau_1$ and $\tau_2$ are chosen to provide the necessary phase boost at the fundamental frequency.
Parameter design for the proposed PLL involves selecting appropriate bandwidths for LADRC and gain for FFSOGI. For the grid-connected inverter system, key parameters are listed in the table below:
| Symbol | Parameter | Value |
|---|---|---|
| $P_{out}$ | Rated Power | 2 kW |
| $U_{dc}$ | DC Voltage | 300 V |
| $f_{sw}$ | Switching Frequency | 10 kHz |
| $f_s$ | Sampling Frequency | 20 kHz |
| $L_1$ | Inverter-side Inductance | 3 mH |
| $L_2$ | Grid-side Inductance | 1 mH |
| $C$ | Filter Capacitance | 15 μF |
| $k_d$ | Active Damping Coefficient | 0.1 |
| $k_{PWM}$ | PWM Gain | 300 |
| $k_p$ (QPR) | Proportional Coefficient | 0.057 |
| $k_r$ (QPR) | Resonant Coefficient | 7.2 |
| $\omega_c$ (QPR) | Control Bandwidth | $\pi$ rad/s |
| $k_{p-PLL}$ | PLL Proportional Coefficient | 4.36 |
| $k_{i-PLL}$ | PLL Integral Coefficient | 1884.2 |
Using impedance analysis, we compare the Bode plots of $Z_{out-PLL}$, $Z_{out}$, and the impedance with the proposed PLL, denoted $Z_{FFSOGI-LPLL}$. The results show that $Z_{FFSOGI-LPLL}$ significantly improves phase margin at crossover frequencies. For instance, with grid impedance $L_g = 10.4$ mH (short-circuit ratio SCR = 3), the phase margin increases by approximately 50.9° compared to traditional PLL. With $L_g = 20.8$ mH (SCR = 1.5), the increase is about 82.4°, and with $L_g = 31.2$ mH (SCR = 1), it is about 96.5°. This enhancement ensures system robustness under weak grid conditions.
To validate the effectiveness of the proposed method, simulations and experiments are conducted. In simulation, a single-phase LCL grid-connected inverter model is built in MATLAB/Simulink. Under traditional PLL control, with $L_g = 2.6$ mH, the grid current $i_2$ remains stable. However, as $L_g$ increases to 5.2 mH, total harmonic distortion (THD) reaches 4.93%, nearing the grid code limit. At $L_g = 10.4$ mH, severe oscillation occurs, making grid connection infeasible. In contrast, with the proposed novel PLL control, at $L_g = 20.8$ mH, the system shows minimal distortion, and even at $L_g = 31.2$ mH, THD remains at 1.14%, meeting grid requirements. Additionally, the phase alignment between grid voltage and current is maintained, ensuring unity power factor operation.
Experimental validation is performed on a 2 kW single-phase LCL grid-connected inverter platform. Under traditional PLL with $L_g = 5.2$ mH, grid current exhibits significant distortion, and the system disconnects at higher impedances. With the novel PLL, stable operation is achieved even at $L_g = 10.4$ mH and $L_g = 31.2$ mH. Dynamic tests show that during load changes from full to half load, the system adjusts within half a grid cycle, demonstrating good dynamic performance. These results confirm that the proposed PLL control structure effectively addresses stability issues in weak grids, enhancing adaptability to wide grid impedance variations.
In conclusion, this paper addresses the instability problem of LCL-type grid-connected inverters in weak grids by proposing a novel PLL structure based on LADRC and FFSOGI. From an impedance perspective, the introduction of PLL reduces the phase of the inverter output impedance, decreasing stability margin as grid impedance increases. The proposed structure combines the disturbance rejection capability of LADRC with the accurate orthogonal signal generation of FFSOGI, reshaping the inverter output impedance phase to enhance phase margin. This allows for stable frequency and phase synchronization control, broadening the system’s adaptability to grid impedance. Simulation and experimental results confirm that the novel PLL offers good transient response and steady-state filtering, enabling precise phase-locking and impedance reshaping in weak grids. Future work may explore extension to three-phase systems and further optimization for extreme grid conditions.
The stability of on-grid inverters is paramount for modern power systems. Our approach directly contributes to improving the reliability of on-grid inverters in weak grid environments. By integrating advanced control techniques, the proposed method ensures that on-grid inverters can maintain synchronization and power quality even under adverse grid conditions. This is crucial for the widespread deployment of renewable energy sources, where on-grid inverters play a pivotal role in interfacing distributed generation with the main grid. The impedance reshaping capability of our novel PLL specifically enhances the robustness of on-grid inverters, making them less susceptible to grid impedance variations and harmonic distortions.
Further analysis of the impedance characteristics reveals that the proposed PLL effectively mitigates the negative impedance effect introduced by traditional PLLs. The mathematical formulation of the output impedance with the novel PLL can be expressed as:
$$Z_{FFSOGI-LPLL}(s) = Z_{out}(s) – Z_{PLL,eff}(s)$$
where $Z_{PLL,eff}(s)$ is the effective impedance of the proposed PLL, which is designed to have a less detrimental phase impact. The redesign of the PLL loop gain ensures that the crossover frequency occurs where the phase margin is sufficient. The linear active disturbance rejection control component actively estimates and compensates for disturbances, which include grid voltage harmonics and imbalances, thereby reducing the q-axis voltage fluctuations that drive the PLL. This results in a more stable phase angle estimate and, consequently, a more favorable output impedance profile for the on-grid inverter.
The FFSOGI component provides an additional layer of filtering and frequency adaptability. Its fixed-frequency operation eliminates the need for frequency adaptation loops, simplifying the design while maintaining accuracy under nominal frequency variations. The orthogonal signals generated by FFSOGI are used to compute the q-axis voltage, which is fed to the LADRC. This combination ensures that even in the presence of grid harmonics, the PLL can accurately track the fundamental phase. The phase compensation block corrects any residual phase errors, ensuring that the on-grid inverter operates at the desired power factor.
To quantify the improvement, we can define the stability margin enhancement as the increase in phase margin at the impedance crossover frequency. For a given grid impedance $L_g$, the crossover frequency $f_c$ is where $|Z_{out-PLL}(j2\pi f_c)| = |Z_g(j2\pi f_c)|$. The phase margin PM is:
$$PM = 180^\circ + \angle Z_{out-PLL}(j2\pi f_c) – \angle Z_g(j2\pi f_c)$$
With the proposed PLL, the phase of $Z_{FFSOGI-LPLL}$ at $f_c$ is higher, leading to a larger PM. The following table summarizes the phase margin improvements for different grid impedances:
| Grid Impedance $L_g$ (mH) | SCR | Traditional PLL PM | Proposed PLL PM | Improvement |
|---|---|---|---|---|
| 10.4 | 3 | -10.0° | 40.9° | 50.9° |
| 20.8 | 1.5 | -47.0° | 35.4° | 82.4° |
| 31.2 | 1 | -62.0° | 34.5° | 96.5° |
These values demonstrate the substantial stability gains achieved by the novel PLL, enabling the on-grid inverter to operate reliably in increasingly weak grids.
In terms of control parameter selection, the LADRC parameters are tuned based on bandwidth concepts. For the PLL application, the controller bandwidth $\omega_{c1}$ is set relative to the desired PLL bandwidth. Typically, the PLL bandwidth $f_{BW}$ is chosen based on the trade-off between dynamic response and noise rejection. For a target $f_{BW} = 250$ Hz, we set $\omega_{c1} = 2\pi \times 250$ rad/s. Then, $\omega_{01} = 4\omega_{c1} = 2\pi \times 1000$ rad/s. The observer gains are calculated as:
$$\beta_1 = 2 \omega_{01}, \quad \beta_2 = \omega_{01}^2$$
The control gain $b_0$ is chosen to normalize the plant gain, often set to 1 for simplicity. The LSEF gain $k_{P1}$ is then designed to achieve the desired closed-loop dynamics. For the FFSOGI, the gain $k=1.63$ ensures a fast settling time without excessive overshoot. These parameter choices are validated through frequency response analysis and time-domain simulations.
The robustness of the proposed control strategy is further analyzed by considering variations in grid conditions. The on-grid inverter must maintain stability under grid voltage sags, swells, harmonics, and frequency deviations. The LADRC’s disturbance estimation capability allows it to adapt to such variations without requiring explicit feedforward compensation. The FFSOGI’s fixed-frequency design ensures that orthogonal signal generation remains accurate even during frequency transients, provided the deviation is within allowable limits (e.g., ±0.2 Hz). The phase compensation block adjusts for small phase errors, ensuring that the on-grid inverter remains synchronized. This comprehensive approach makes the system highly robust, which is essential for real-world applications where grid conditions are often unpredictable.
In summary, the novel PLL structure proposed in this paper represents a significant advancement in the control of grid-connected inverters. By leveraging the strengths of LADRC and FFSOGI, it addresses the critical stability challenges posed by weak grids. The impedance reshaping effect enhances phase margin, allowing the inverter to tolerate larger grid impedances without instability. Simulation and experimental results corroborate the theoretical analysis, showing improved current quality and stable operation under weak grid conditions. This work contributes to the broader goal of integrating renewable energy sources into the grid by enhancing the performance and reliability of on-grid inverters. Future research could explore the application of this approach to three-phase systems, multi-inverter configurations, and integration with energy storage systems for further grid support functionalities.