As a researcher focused on power electronics, I am constantly confronted with the core challenge of modern wind energy integration: ensuring stable and high-quality power injection into the grid despite inherent intermittency and disturbance. The grid tied inverter serves as the critical final gateway in a permanent magnet synchronous generator (PMSG)-based direct-drive wind power system. Its performance directly dictates grid power quality and system reliability. Traditional vector control strategies using dual-loop PI controllers, while prevalent, exhibit limitations in dynamic response, disturbance rejection, and harmonic suppression, especially under realistic grid conditions characterized by voltage sags, swells, and harmonic distortions. This article details my investigation and proposal for a superior control strategy that synergistically combines a second-order Linear Active Disturbance Rejection Controller (LADRC) for the voltage outer loop and a Quasi-Proportional Resonant (Quasi-PR) controller for the current inner loop, specifically designed to enhance the performance of the wind power grid tied inverter.
1. The Control Challenge for Grid-Tied Inverters in Wind Systems
The topology of a standard two-level voltage source grid tied inverter is the workhorse for this application. The primary control objectives are twofold: first, to maintain a stable DC-link voltage despite fluctuations from the generator side, and second, to inject sinusoidal currents into the grid with low total harmonic distortion (THD) and specified power factor. The mathematical model of the system in the synchronous rotating (d-q) frame is given by:
$$
\begin{align*}
L\frac{di_{gd}}{dt} &= u_{gd} – R i_{gd} + \omega L i_{gq} – e_{gd} \\
L\frac{di_{gq}}{dt} &= u_{gq} – R i_{gq} – \omega L i_{gd} – e_{gq} \\
C\frac{dU_{dc}}{dt} &= I_0 – \frac{3}{2}(S_d i_{gd} + S_q i_{gq})
\end{align*}
$$
Where \(i_{gd}, i_{gq}\) and \(e_{gd}, e_{gq}\) are grid currents and voltages in the d-q frame, \(u_{gd}, u_{gq}\) are inverter output voltages, \(L\) and \(R\) are the filter inductance and resistance, \(U_{dc}\) is the DC-link voltage, and \(\omega\) is the grid angular frequency. The conventional PI-based vector control decouples the d and q current dynamics using feedforward terms. However, its performance is inherently linked to the accuracy of system parameters (\(L, R\)). Furthermore, PI controllers in the rotating frame require multiple coordinate transformations and offer poor disturbance rejection against unmodeled dynamics and external grid perturbations. This motivates the search for a more robust and structurally simpler alternative.
2. Core of the Proposed Strategy: Linear Active Disturbance Rejection Control (LADRC)
My approach for the voltage outer loop leverages the philosophy of LADRC. The central idea is to treat the aggregate effect of all uncertainties—including parameter variations, coupling terms, and external disturbances—as a “total disturbance,” estimate it in real-time, and actively cancel it. This renders the plant into a simple cascade of integrators, simplifying controller design. For the DC-link voltage loop, which is a second-order system, I design a second-order LADRC.
First, I reformulate the DC-link voltage dynamics from the model. By differentiating and rearranging, the relationship can be expressed as:
$$
\frac{d^2U_{dc}}{dt^2} = f + b_0 u
$$
Here, \(u = i_{gd}^*\) (the d-axis current reference) is the control input, \(b_0\) is a known approximate gain, and \(f\) encapsulates the total disturbance mentioned above, which is now an extended state variable \(x_3 = f\). The state-space model becomes:
$$
\begin{align*}
\dot{x}_1 &= x_2 \\
\dot{x}_2 &= x_3 + b_0 u \\
\dot{x}_3 &= h \\
y &= x_1
\end{align*}
$$
where \(x_1 = U_{dc}\), \(x_2 = \dot{U}_{dc}\), and \(h\) is the derivative of the disturbance.
The Linear Extended State Observer (LESO) is the heart of LADRC. A third-order LESO is constructed to estimate all three states, including the disturbance:
$$
\begin{align*}
\dot{z}_1 &= z_2 – l_1(z_1 – U_{dc}) \\
\dot{z}_2 &= z_3 – l_2(z_1 – U_{dc}) + b_0 u \\
\dot{z}_3 &= -l_3(z_1 – U_{dc})
\end{align*}
$$
where \(z_1, z_2, z_3\) estimate \(x_1, x_2, x_3\) respectively. By placing all observer poles at \(-\omega_o\), the observer gains are simplified to \(l_1 = 3\omega_o, l_2 = 3\omega_o^2, l_3 = \omega_o^3\). The single parameter \(\omega_o\), the observer bandwidth, dictates the estimation speed and noise sensitivity.
The Linear State Error Feedback (LSEF) law then uses these estimates to generate the control signal. For a second-order plant simplified to \(\ddot{y} = u_0\), a PD controller suffices:
$$
u_0 = k_p(U_{dc}^* – z_1) – k_d z_2
$$
where \(U_{dc}^*\) is the reference voltage. Placing the two closed-loop poles at \(-\omega_c\) gives \(k_p = \omega_c^2\) and \(k_d = 2\omega_c\). The final control law for the grid tied inverter is:
$$
u = i_{gd}^* = \frac{u_0 – z_3}{b_0}
$$
This elegantly compensates for the estimated total disturbance \(z_3\) in real-time. The parameter tuning for the voltage loop is thus reduced to adjusting just two intuitive parameters: the observer bandwidth \(\omega_o\) and the controller bandwidth \(\omega_c\).
3. Enhancing Current Quality: Quasi-Proportional Resonant (Quasi-PR) Control
For the current inner loop, I abandon the rotating d-q frame and its associated decoupling complexity. Instead, I employ Quasi-PR controllers directly in the stationary (α-β) frame. This is highly effective for tracking sinusoidal references. The transfer function of a Quasi-PR controller is:
$$
G_{QPR}(s) = K_p + \frac{2K_r\omega_c s}{s^2 + 2\omega_c s + \omega_0^2}
$$
Where \(K_p\) is the proportional gain, \(K_r\) is the resonant gain, \(\omega_0\) is the fundamental frequency (e.g., \(100\pi\) rad/s), and \(\omega_c\) is the cutoff frequency that determines the bandwidth around the resonant frequency. Unlike an ideal PR controller with infinite gain at \(\omega_0\), the Quasi-PR offers high but finite gain, which improves stability. Crucially, it provides zero phase and magnitude error at \(\omega_0\), enabling near-perfect tracking of the fundamental grid current. This directly translates to lower current THD for the grid tied inverter. The controller’s frequency response is shaped by its three parameters, as summarized in the analysis below:
| Parameter | Effect on Controller Performance |
|---|---|
| \(K_p\) | Affects the overall gain and dynamic response across all frequencies. A higher \(K_p\) improves response speed but may reduce stability margins. |
| \(K_r\) | Determines the peak gain at the resonant frequency \(\omega_0\). Higher \(K_r\) reduces steady-state error but can amplify noise and harmonics if too large. |
| \(\omega_c\) | Sets the bandwidth around \(\omega_0\). A larger \(\omega_c\) makes the controller less sensitive to grid frequency variations but reduces the selectivity of harmonic rejection. |
4. Integrated Control Scheme for the Grid-Tied Inverter
The complete, proposed control architecture for the wind power grid tied inverter integrates the two advanced controllers into a cohesive double-loop structure, offering a clear advantage over the conventional method.
| Control Loop | Conventional Strategy | Proposed Strategy | Key Advantage |
|---|---|---|---|
| Outer Loop (Voltage) | PI Controller in d-q frame | Second-order LADRC | Superior disturbance rejection, faster recovery from DC-link voltage transients, robust to internal parameter changes. |
| Inner Loop (Current) | PI Controller in d-q frame with decoupling | Quasi-PR Controller in α-β frame | Eliminates need for decoupling and multiple transformations; provides inherent zero-error tracking at grid frequency; superior harmonic suppression. |
The operational principle is as follows: The DC-link voltage \(U_{dc}\) is compared with its reference \(U_{dc}^*\). The error is processed by the LADRC voltage controller, which generates the active current reference \(i_{\alpha}^*\) (after setting the reactive reference \(i_{\beta}^* = 0\) for unity power factor). The actual grid currents \(i_{\alpha}, i_{\beta}\) are compared with their references. These errors are fed into two identical Quasi-PR controllers (one for each α and β axis). The outputs of these controllers, after compensating for the grid voltage (\(e_{\alpha}, e_{\beta}\)), form the voltage reference signals \(u_{\alpha}^*, u_{\beta}^*\) for the Space Vector Pulse Width Modulation (SVPWM) block, which finally generates the gating signals for the inverter’s power switches. This structure is notably more straightforward and robust than the traditional cascade PI control.
5. Simulation Analysis and Performance Validation
To validate the superiority of the proposed LADRC+Quasi-PR strategy, I conducted comprehensive simulations in MATLAB/Simulink, comparing it directly against the traditional dual-loop PI control. The system parameters for the grid tied inverter are listed below:
| Parameter | Value |
|---|---|
| Grid Voltage (Line-to-Line) | 690 V |
| Grid Frequency | 50 Hz |
| DC-Link Voltage Reference \(U_{dc}^*\) | 1800 V |
| DC-Link Capacitor \(C\) | 4700 µF |
| Filter Inductance \(L\) | 3 mH |
| Filter Resistance \(R\) | 0.2 Ω |
| Switching Frequency \(f_s\) | 10 kHz |
The controllers were tuned as follows: For LADRC, \(\omega_o = 2200\) rad/s and \(\omega_c = 500\) rad/s. For the Quasi-PR, \(K_p = 5\), \(K_r = 10\), and \(\omega_c = 3.14\) rad/s (for a ~0.5 Hz bandwidth).
Scenario 1: Normal Operation (Start-up)
The dynamic response of the DC-link voltage during start-up is a critical test. Under the proposed control, the DC voltage rises to its reference of 1800 V with a negligible overshoot of less than 10 V and a settling time of approximately 50 ms. In stark contrast, the traditional PI control causes an overshoot of about 100 V and takes nearly 200 ms to settle. This demonstrates the exceptional dynamic regulation capability of the LADRC-based outer loop for the grid tied inverter.
Scenario 2: Steady-State Current Quality
The primary goal of the inner loop controller is to produce high-quality grid current. The Fast Fourier Transform (FFT) analysis of the steady-state grid current reveals a significant improvement. The traditional PI control yields a current THD of 2.31%. The proposed Quasi-PR control reduces the THD to 1.51%. The current waveform under Quasi-PR control is noticeably more sinusoidal, highlighting its efficacy in harmonic suppression for the grid tied inverter.
Scenario 3: Grid Voltage Disturbance (Swell)
The true test of robustness is performance under grid disturbances. A 10% voltage swell (from 690V to 760V) was applied for 1 second. The results are summarized below:
| Performance Metric | Traditional PI Control | Proposed LADRC+QPR |
|---|---|---|
| DC Voltage Overshoot at Swell Onset | ~20 V | ~10 V |
| Settling Time after Swell Onset | ~60 ms | ~30 ms |
| DC Voltage Dip at Swell End | ~20 V | ~10 V |
| Settling Time after Swell End | ~70 ms | ~28 ms |
The LADRC controller’s ability to rapidly estimate and cancel the disturbance caused by the grid voltage change is clearly superior. The grid tied inverter with the proposed strategy exhibits minimal deviation and a faster recovery, ensuring stable power delivery even during grid faults.
6. Conclusion and Outlook
This detailed exploration presents a compelling case for adopting a combined LADRC and Quasi-PR control strategy for wind power grid tied inverters. The proposed architecture directly addresses the key limitations of conventional PI-based vector control. The second-order LADRC for the DC-link voltage loop provides remarkable robustness and fast dynamic response by actively rejecting both internal and external disturbances. Simultaneously, the stationary-frame Quasi-PR current controller simplifies the control structure, eliminates cross-coupling concerns, and significantly improves the quality of the injected current by minimizing harmonic distortion.
Simulation results under normal and disturbed grid conditions consistently demonstrate the superiority of this approach: faster settling times, smaller voltage deviations, and lower current THD. This translates to a more reliable, efficient, and grid-friendly wind energy conversion system. Future work will involve implementing this algorithm on a real-time digital signal processor (DSP) to validate its performance on a hardware prototype, further exploring its adaptability to weak grid conditions and its integration with grid-supporting functions like fault ride-through. The proposed strategy offers a potent and elegant solution for enhancing the next generation of intelligent and resilient grid tied inverters.