With the rapid development of society, distributed generation technologies have become a focal point of current research. The grid tied inverter, as a critical interface unit between distributed generation systems and the power grid, directly impacts the grid connection performance. Currently, most grid tied inverters domestically employ a single DSP control chip for controller implementation. However, due to limitations in analog-to-digital conversion, sampling frequency, and other factors, the real-time processing and functional requirements of DSPs are not fully met, making it challenging to accommodate the high-power grid integration demands. In this work, I design a grid tied inverter based on a dual-CPU control architecture utilizing DSP and FPGA. The DSP microprocessor chip serves as the main control chip, while the FPGA logic controller acts as an auxiliary control chip. This combination offers fast computation speed and precise control, not only meeting complex computational needs but also significantly enhancing the efficiency and real-time performance of the control system. The control strategy employs a dual-loop voltage and current instantaneous value control based on PI regulation, which boasts advantages such as strong robustness, simple structure, and high reliability. This article details the hardware and software design process of the main circuit and control circuit for a three-phase grid tied inverter, and a 5kW experimental prototype is constructed. Experimental results demonstrate that the grid tied inverter is reasonably designed, operates reliably, outputs stable current, meets various design specifications, and holds high practical and promotional value.
The grid tied inverter consists of two main parts: the power circuit and the control circuit. The power circuit includes the DC/AC inverter circuit and the LCL filter circuit. The direct current output from distributed sources is converted into alternating current through boosting, inversion, and filtering before being fed into the grid. The control circuit primarily comprises the main control circuit, signal sampling and conditioning circuit, PWM drive circuit, and protection circuit. It detects signals from the power circuit, performs corresponding control computations and space vector modulation via DSP and FPGA, and generates PWM pulses to drive the power switches. The overall design structure is illustrated in Figure 1.
To meet high-power requirements and improve conversion efficiency, the power circuit of the grid tied inverter adopts an LCL-type three-phase full-bridge topology. In this configuration, Udc represents the input DC voltage of the grid tied inverter, Cdc is the input DC bus filtering capacitor, Ta1 to Tc2 are the six IGBT switches of the three-phase inverter bridge, and the LCL filter consists of the inverter-side inductance L1, filter capacitor Cf, and grid-side inductance L2. This topology is widely used in modern grid tied inverters due to its superior harmonic attenuation capabilities compared to simple L filters.
Power Circuit Design and Component Selection
The design of the power circuit is crucial for the performance and reliability of the grid tied inverter. Key components include the IGBT modules, the DC-link capacitor, and the LCL filter. Proper parameter selection ensures efficient operation, minimal harmonics, and compliance with grid standards.
IGBT Selection
In the circuit design, the rated power P of the grid tied inverter is 5kW, with an output line voltage of 380V. The peak phase current Ip can be calculated as:
$$ I_p = \frac{2P}{\sqrt{3} U_{line}} = \frac{2 \times 5000}{\sqrt{3} \times 380} \approx 10.74 \, \text{A} $$
Therefore, under rated power, the peak current through each IGBT is approximately 35.81A. Considering a 20% margin, the maximum voltage across the switches is:
$$ U_{dmax} = 1.2 \times U_{dc} = 1.2 \times 700 = 840 \, \text{V} $$
Based on these calculations, the IGBT module selected is FF300R12KS4, which has a voltage rating of 1200V and a current rating of 300A, providing sufficient safety margins. This choice ensures the grid tied inverter can handle transient overloads and voltage spikes commonly encountered in grid applications.
DC-Link Capacitor Design
The DC-link capacitor, also known as the support capacitor, stabilizes the DC bus voltage and buffers energy between the source and the inverter. According to dynamic response requirements, under rated operation, when the inverter load suddenly increases by 50%, the maximum DC voltage fluctuation should be less than 5%. The required capacitance can be derived from energy balance:
$$ \frac{1}{2} C_{dc} \Delta U_{dc}^2 \geq 50\% \times P \times t $$
Where t is the response time. Assuming a typical response time of 10 ms, we get:
$$ C_{dc} \geq \frac{2 \times 0.5 \times 5000 \times 0.01}{(0.05 \times 700)^2} \approx 209 \, \mu\text{F} $$
Considering factors such as cost, dynamic response characteristics, and reliability, aluminum electrolytic capacitors with a capacitance of 420 μF and a voltage rating of 1000V are chosen. This provides adequate energy storage and minimizes voltage ripple, essential for stable operation of the grid tied inverter.
LCL Filter Parameter Design
The LCL filter is employed to attenuate switching harmonics generated by the grid tied inverter, ensuring that the output current meets grid quality standards. The design involves selecting the total inductance, dividing it between inverter-side and grid-side inductors, and choosing the filter capacitor.
Total Inductance Selection
From the perspective of fundamental current, the LCL filter can be equivalent to a single L-type filter with total inductance Lx = L1 + L2. The design must balance filtering requirements with minimizing magnetic material usage and device volume. Under purely inductive conditions, the maximum output voltage of the three-phase bridge arms must satisfy:
$$ L_x \leq \frac{\sqrt{3} U_{dc} / \sqrt{2} – U_g}{I_g} $$
Where Ug is the grid phase voltage and Ig is the grid current. For our design, with Udc = 700V, Ug = 220V (phase voltage), and Ig = 10.74A, we calculate Lx ≤ 15.2 mH. A value of 6 mH is chosen to provide good filtering while keeping losses manageable.
Inverter-Side Inductance L1 Selection
With total inductance Lx fixed, the ratio L1/L2 significantly affects the system’s filtering performance. A higher ratio enhances the attenuation of switching-frequency harmonics by L1, but it also increases the core size and harmonic current amplitude. To minimize harmonic current amplitude and achieve optimal filtering, the ratio L1/L2 is typically set between 3 and 7. For this grid tied inverter, we select L1 = 5 mH and L2 = 1 mH, giving a ratio of 5.
Filter Capacitor Design
The filter capacitor Cf is crucial for bypassing high-frequency harmonics. However, excessively large capacitance increases reactive power, leading to higher system losses. To maintain conversion efficiency, the reactive power of the filter capacitor should be less than 5% of the system’s rated power. Thus:
$$ C_f \leq \frac{0.05 \times P}{3 \times 2\pi f_1 U_g^2} $$
Where f1 = 50 Hz is the grid fundamental frequency. Substituting values yields Cf ≤ 8.2 μF. Additionally, to eliminate resonance peaks in low or high-frequency bands, the resonant frequency fh of the LCL filter should satisfy 10f1 < fh < fs/2, where fs is the switching frequency (e.g., 10 kHz). The resonant frequency is given by:
$$ f_h = \frac{1}{2\pi} \sqrt{\frac{L_1 + L_2}{L_1 L_2 C_f}} $$
With L1 = 5 mH, L2 = 1 mH, and Cf = 5 μF, we compute fh ≈ 1.03 kHz, which meets the condition 500 Hz < 1.03 kHz < 5 kHz. This ensures effective damping of resonances and stable operation of the grid tied inverter.
To summarize the LCL filter design, the following table presents the key parameters:
| Parameter | Symbol | Value | Unit |
|---|---|---|---|
| Total Inductance | Lx | 6 | mH |
| Inverter-Side Inductance | L1 | 5 | mH |
| Grid-Side Inductance | L2 | 1 | mH |
| Filter Capacitance | Cf | 5 | μF |
| Resonant Frequency | fh | 1.03 | kHz |
Control System Design and Strategy
The control system is the brain of the grid tied inverter, ensuring accurate current injection into the grid with proper phase and waveform. The proposed control scheme uses a dual-loop strategy with an outer voltage loop and an inner current loop, both employing digital PI regulators. The voltage outer loop regulates the DC-link voltage, and its output serves as the reference for the q-axis current inner loop. The current inner loop controls the grid current’s phase and waveform based on the reference, producing PWM signals to drive the power switches. This approach enhances the dynamic response and stability of the grid tied inverter.
The control system diagram illustrates the overall structure. In three-phase systems, it is common to transform variables from the abc stationary frame to the dq rotating frame using Park transformation. This simplifies control by converting AC quantities into DC quantities. The transformation equations are:
$$ \begin{bmatrix} i_d \\ i_q \end{bmatrix} = \frac{2}{3} \begin{bmatrix} \cos(\theta) & \cos(\theta – 2\pi/3) & \cos(\theta + 2\pi/3) \\ -\sin(\theta) & -\sin(\theta – 2\pi/3) & -\sin(\theta + 2\pi/3) \end{bmatrix} \begin{bmatrix} i_a \\ i_b \\ i_c \end{bmatrix} $$
Where θ is the grid voltage phase angle obtained from a phase-locked loop (PLL). In the dq frame, the d-axis typically corresponds to active power control, while the q-axis corresponds to reactive power control. For unity power factor operation, the q-axis current reference is set to zero.
However, the d and q axes are coupled due to cross-coupling terms in the system model. To achieve independent control, decoupling is necessary. Current feedback decoupling control is employed, which uses PI regulators to compensate for errors between feedback and reference currents, effectively linearizing the system. The decoupled current inner loop control block diagram for the d-axis is shown below. Similar principles apply to the q-axis due to symmetry.
The transfer function of the current loop can be derived considering sampling delay and PWM delay. Let Ts be the current sampling period, KP and Ki be the PI parameters, and KPWM be the inverter gain. The open-loop transfer function Gol(s) is:
$$ G_{ol}(s) = K_{PWM} \cdot \frac{K_P s + K_i}{s} \cdot \frac{1}{1 + T_s s} \cdot \frac{1}{1 + 0.5 T_s s} \cdot \frac{1}{L_1 s + R} $$
Where R represents the equivalent resistance. Using frequency domain methods, the PI parameters can be tuned to achieve desired bandwidth and phase margin. For instance, setting the crossover frequency at one-tenth of the switching frequency (e.g., 1 kHz) and a phase margin of 60° yields KP = 0.5 and Ki = 100. These values ensure fast response and stability for the grid tied inverter.
The voltage outer loop is designed similarly but with slower dynamics to avoid interference with the current loop. Its output provides the d-axis current reference, which is derived from power balance between DC and AC sides. The control law ensures that the DC-link voltage remains constant despite load variations, a critical function for any grid tied inverter.
Hardware System Design of the Grid Tied Inverter
The hardware implementation of the grid tied inverter is based on a dual-CPU architecture combining DSP and FPGA. This architecture leverages the strengths of both processors: DSP excels in complex mathematical computations, while FPGA offers parallel processing and high-speed logic control. The overall system structure includes the power circuit and control circuit, with the latter comprising the main control circuit, signal sampling and conditioning circuit, PWM drive circuit, and protection circuit.
Main Control Circuit Design
The main control circuit uses TMS320F28335 DSP as the primary controller and EP2C35F672C6N FPGA as the auxiliary controller. The DSP handles high-precision data acquisition, voltage outer loop control, and communication tasks. It executes algorithms in C language, providing rapid processing capabilities. The FPGA, programmed with VHDL, implements hardware circuits for protection, control, and data exchange. The two processors communicate via the DSP’s external asynchronous interface (XINTF), enabling data sharing and functional distribution. This setup enhances system reliability and real-time performance, crucial for a grid tied inverter operating in demanding environments.
Signal Sampling and Conditioning Circuit
Accurate signal sampling is vital for effective control of the grid tied inverter. The sampling circuit measures DC-side voltage and current, bus-side voltage and current, and three-phase grid-side voltage and current. Sensors convert high-voltage/current signals to low-voltage signals, which are then amplified and limited by conditioning circuits before being sent to the DSP. For example, voltage sensors like CV3-500 are used, and operational amplifiers such as OP284EPZ process the signals. The grid phase voltage sampling circuit includes a gain stage and a level-shifting stage to match the ADC input range of the DSP. This ensures precise measurement, enabling the grid tied inverter to respond accurately to grid conditions.
The following table summarizes the key components used in the sampling circuit:
| Signal Type | Sensor/Component | Specifications |
|---|---|---|
| DC Voltage | Voltage Divider + Op-Amp | Scale factor: 1/100, Offset: 1.5V |
| Grid Voltage | CV3-500 Voltage Sensor | Input: 0-500V AC, Output: 0-5V |
| Grid Current | Hall Effect Current Sensor | Input: 0-20A AC, Output: 0-5V |
| Signal Conditioning | OP284EPZ Op-Amp | Low noise, high precision |
PWM Drive Circuit
The PWM signals generated by the FPGA have low power and cannot directly drive IGBTs. Thus, a drive circuit amplifies these signals. The drive module employs 2SD106AI, which operates in half-bridge mode. It includes dead-time generation via external RC networks (default 1.1 μs) and provides isolation and protection features. The input A receives the PWM signal, while input B is an enable signal. When enabled high (15V), the IGBT turns on; when low, it turns off. Fault detection pulls the status output to ground, ensuring safe operation of the grid tied inverter.
Protection Circuit
Protection circuits are essential to safeguard the grid tied inverter from faults such as overcurrent, overvoltage, and short circuits. The design includes current limiting, voltage monitoring, and FPGA signal protection. When a fault is detected, the circuit latches the error signal and blocks gate signals, turning off all six switches to disconnect the main circuit. This prevents damage to components and ensures grid safety. The protection mechanism enhances the reliability of the grid tied inverter, making it suitable for continuous operation in distributed generation systems.
Software Design and Implementation
The software design for the grid tied inverter leverages the dual-CPU architecture to distribute tasks efficiently. The DSP handles high-level control algorithms, while the FPGA manages real-time PWM generation and protection. This division of labor optimizes performance and responsiveness.
Main Program Flow
After power-up, the DSP initializes peripherals and enters an AD interrupt service routine. In the interrupt, sampled signals are filtered, converted to physical values, and used in control strategy computations. The processed modulation signals are then transmitted to the FPGA via SPI communication. The main program flow ensures that control updates occur at fixed intervals, typically synchronized with the PWM frequency. This structured approach maintains stability and accuracy in the grid tied inverter.
SPI Communication
The TMS320F28335 DSP includes an SPI module, which is configured as the master to provide clock signals. The FPGA acts as the slave, with its SPI module implemented using Verilog HDL. In master-slave mode, data is shifted out on one edge of SPICLK and shifted in on the opposite edge. When data is written to the SPI data register (SPIDAT) and the transmit buffer (SPITXBUF), transmission begins with the most significant bit. This serial communication enables fast data exchange between DSP and FPGA, crucial for coordinating control actions in the grid tied inverter.
Phase-Locked Loop (PLL)
A phase-locked loop is employed to synchronize the grid tied inverter with the grid voltage. The DQ-PLL method is used, where the q-axis component of the grid voltage is proportional to the phase error. A PI controller adjusts the estimated frequency and phase to eliminate steady-state errors. The PLL ensures accurate grid synchronization, which is fundamental for injecting current in phase with the grid voltage. The implementation involves Park transformation of grid voltages and PI regulation of the q-axis component. This robust PLL design enables the grid tied inverter to operate reliably under varying grid conditions.
The PLL dynamics can be described by the following equations:
$$ \theta = \int (\omega_{nom} + \Delta \omega) \, dt $$
$$ \Delta \omega = K_{p,PLL} e + K_{i,PLL} \int e \, dt $$
$$ e = u_{q} \approx U_g \sin(\theta_{grid} – \theta) $$
Where ωnom is the nominal grid frequency, and e is the error signal. Proper tuning of Kp,PLL and Ki,PLL ensures fast and stable locking, essential for the grid tied inverter’s performance.
Experimental Results and Analysis
To validate the design, a 5 kW three-phase full-bridge grid tied inverter prototype was constructed. Tests were conducted using a FLUKE435 power quality analyzer to measure output voltage, current, harmonics, and other parameters. The results demonstrate the effectiveness of the proposed dual-CPU architecture and control strategy.
The three-phase output voltage waveforms show balanced voltages with phase values approximately 233 V RMS, indicating proper inverter operation. The three-phase output current waveforms exhibit currents around 12 A RMS with minimal imbalance, confirming effective current control. Harmonic analysis reveals that the total harmonic distortion (THD) of the phase current is below 4%, meeting standard requirements such as IEEE 1547. For instance, the B-phase current THD is measured at 3.7%, which is within acceptable limits for grid tied inverters.
The following table summarizes key experimental measurements:
| Parameter | Phase A | Phase B | Phase C | Unit |
|---|---|---|---|---|
| Voltage (RMS) | 233.2 | 231.9 | 232.0 | V |
| Current (RMS) | 11.0 | 13.0 | 12.0 | A |
| Current THD | 3.5% | 3.7% | 3.6% | % |
| Power Factor | 0.99 | 0.99 | 0.99 | — |
Dynamic response tests were also performed by applying step changes in load. The grid tied inverter demonstrated fast recovery with minimal overshoot, thanks to the well-tuned PI controllers. The DC-link voltage remained stable within 2% of its setpoint, showcasing the robustness of the voltage outer loop. These results affirm that the grid tied inverter design meets performance criteria for grid integration.
Conclusion
In this work, a three-phase grid tied inverter based on a dual-CPU architecture using DSP and FPGA has been designed and implemented. The system employs an LCL filter for harmonic attenuation and a dual-loop control strategy with PI regulators for precise current and voltage regulation. The hardware design incorporates robust sampling, driving, and protection circuits, while the software leverages the strengths of both processors for efficient control. Experimental results from a 5 kW prototype confirm that the grid tied inverter operates stably, with low harmonic distortion and good dynamic response. This design offers a scalable solution for high-power grid tied inverter applications in distributed generation, highlighting its practical value and potential for widespread adoption. Future work may focus on enhancing control algorithms for unbalanced grid conditions and integrating advanced features like reactive power support.