In modern power electronics, the three phase inverter is a critical component in various applications such as renewable energy systems, motor drives, and grid-connected interfaces. The demand for higher efficiency and power density has driven the adoption of wide-bandgap semiconductor devices, which enable higher switching frequencies. However, increasing the switching frequency also elevates switching losses, particularly in hard-switched topologies. To address this, soft-switching techniques like zero-voltage switching (ZVS) are employed to minimize these losses. This article presents a novel control strategy for interleaved parallel three phase inverters that achieves full-range ZVS under any power factor condition using current ripple prediction (CRP) theory. The approach utilizes variable switching frequency and discontinuous pulse width modulation (DPWM) to simplify implementation and enhance performance. By eliminating the need for additional sensors or auxiliary circuits, the proposed method offers a cost-effective solution for high-frequency three phase inverter systems.
The interleaved parallel three phase inverter topology consists of two three-phase inverters connected in parallel, sharing a common LCL filter. This configuration reduces current ripple on the grid side and allows for higher power handling. The key challenge in achieving ZVS is ensuring that the inductor current has the appropriate direction during the dead time to discharge the output capacitance of the switches. In a three phase inverter, the coupled nature of the phase currents complicates this process. Traditional methods often require additional hardware, such as zero-crossing detection circuits or resonant networks, which increase complexity and cost. The proposed strategy overcomes these limitations by leveraging CRP to predict the current ripple and adaptively adjust the switching frequency for ZVS under varying load conditions and power factors.
The principle of ZVS in a three phase inverter relies on the inductor current discharging the switch output capacitance before turn-on. For the top switch to achieve ZVS, the inductor current must flow into the midpoint, while for the bottom switch, it must flow out. The CRP method calculates the required current ripple to ensure this discharge occurs. The inductor current ripple $$ \Delta i_x $$ for phase x is derived from the volt-second balance across the inductor. For a three phase inverter using DPWM, only two phases switch at high frequency in each sector, simplifying the analysis. The current ripple can be expressed as:
$$ \Delta i_x = \frac{V_{dc} – v_x}{L_1 f_s} $$
where $$ V_{dc} $$ is the DC bus voltage, $$ v_x $$ is the phase voltage, $$ L_1 $$ is the inverter-side inductance, and $$ f_s $$ is the switching frequency. To achieve ZVS, the current at the switching instant must satisfy:
$$ i_x(t_{on}) < -I_{bias} \quad \text{for top switch turn-on} $$
$$ i_x(t_{off}) > I_{bias} \quad \text{for bottom switch turn-on} $$
where $$ I_{bias} $$ is the minimum discharge current. Combining these conditions with the current ripple prediction, the critical switching frequency for ZVS in each phase can be derived. For example, in the first sector of the DPWM scheme, the critical frequencies for phases b and c are given by:
$$ f_{sb1} = \frac{V_{dc} (3m_b – 2) + 6v_b (1 – m_b)}{6L_1 (I_{bias} + |i_{gb}|)} $$
$$ f_{sc1} = \frac{(V_{dc} – v_c)(1 – m_c)}{3L_1 (I_{bias} + |i_{gc}|)} $$
where $$ m_x $$ is the modulation index for phase x, and $$ i_{gx} $$ is the grid current. The overall system switching frequency is selected as the minimum among the critical frequencies in the active phases to ensure ZVS for all switches while minimizing conduction loss. This adaptive frequency calculation allows the three phase inverter to maintain ZVS across the entire line cycle and under any power factor.
The control strategy for the interleaved parallel three phase inverter involves a closed-loop system that samples grid voltages and currents to compute the modulation indices and switching frequency. A phase-locked loop (PLL) synchronizes with the grid, and a dq-frame controller regulates the active and reactive power. The modulation waves are generated using DPWM, and the switching frequency is updated in real-time based on the CRP calculations. The two inverters share the same modulation waves but with carriers phase-shifted by 180 degrees to achieve interleaving, which reduces the net current ripple. The following table summarizes the key parameters used in the analysis:
| Parameter | Symbol | Value |
|---|---|---|
| DC Bus Voltage | $$ V_{dc} $$ | 400 V |
| Grid Voltage (RMS) | $$ V_{rms} $$ | 110 V |
| Rated Power | $$ S_{max} $$ | 3.5 kVA |
| Inverter-Side Inductance | $$ L_1 $$ | 36 μH |
| Grid-Side Inductance | $$ L_2 $$ | 10 μH |
| Filter Capacitance | $$ C $$ | 4.7 μF |
| Bias Current | $$ I_{bias} $$ | 2 A |
The performance of the proposed three phase inverter control strategy was evaluated through simulations and experiments. Under full load and varying power factors, the inverter maintained ZVS with switching frequencies ranging from 100 kHz to 250 kHz. The inductor currents exhibited the required ripple to discharge the switch capacitances, and the grid currents met harmonic standards. The following table compares the efficiency of the proposed soft-switching three phase inverter with a traditional hard-switched inverter at 50 kHz:
| Load Condition | Proposed Strategy Efficiency | Traditional Hard-Switching Efficiency |
|---|---|---|
| 25% Load | 97.0% | 97.5% |
| 50% Load | 98.2% | 97.8% |
| 75% Load | 98.6% | 98.1% |
| 100% Load | 98.75% | 98.3% |
The power loss analysis reveals that while the proposed method reduces switching losses, it slightly increases conduction losses due to higher current ripple. However, the net efficiency improvement is significant, especially at higher loads. The inverter-side inductor losses are minimized due to the interleaving effect, which cancels out high-frequency ripple components. The core losses in the inductors are calculated using the Steinmetz equation, and the copper losses are derived from the RMS current. The total losses for the three phase inverter are distributed as follows:
$$ P_{total} = P_{cond} + P_{sw} + P_{core} + P_{copper} $$
where $$ P_{cond} $$ is the conduction loss, $$ P_{sw} $$ is the switching loss, $$ P_{core} $$ is the core loss, and $$ P_{copper} $$ is the copper loss. In the proposed strategy, $$ P_{sw} $$ is negligible due to ZVS, but $$ P_{cond} $$ is higher compared to hard-switching. The following equation estimates the conduction loss for a switch:
$$ P_{cond} = I_{rms}^2 R_{ds(on)} $$
where $$ I_{rms} $$ is the RMS current through the switch, and $$ R_{ds(on)} $$ is the on-state resistance. For the three phase inverter, the RMS current is influenced by the modulation scheme and load power factor. The variable switching frequency strategy ensures that the current ripple is controlled to minimize unnecessary losses while maintaining ZVS.
Experimental results on a 3.5 kVA prototype using SiC MOSFETs confirm the feasibility of the control strategy. The three phase inverter achieved ZVS under resistive, inductive, and capacitive loads with power factors ranging from 0 to 1. The dynamic response to load steps was fast, with the switching frequency adjusting within a few milliseconds. The grid currents remained sinusoidal with low distortion, demonstrating the effectiveness of the approach for grid-connected applications. The use of a small LCL filter, enabled by the high switching frequency, reduces the overall size and cost of the three phase inverter system.
In conclusion, the current ripple prediction-based soft-switching method for interleaved parallel three phase inverters offers a robust solution for achieving high efficiency and power density. The adaptive variable switching frequency control ensures ZVS under any power factor condition without additional hardware. This makes the three phase inverter suitable for advanced applications requiring reactive power compensation and wide operating ranges. Future work could focus on optimizing the inductor design and extending the strategy to multi-level three phase inverter topologies.