Inverter technology plays a crucial role in the development and utilization of renewable energy sources such as solar and wind power. Due to advantages like high efficiency, strong stability, and precise output, inverters are widely applied in photovoltaic grid-connected systems and wind power generation. This design presents a single phase inverter based on the EG8010 controller, utilizing a single-phase full-bridge topology to achieve inversion. The system generates unipolar sinusoidal pulse width modulation (SPWM) waves via the EG8010 chip, processes them through a full-bridge circuit and LC filter, and outputs a pure sine wave. Additionally, the circuit incorporates overcurrent and overvoltage protection features to enhance reliability. The single phase inverter design focuses on optimizing performance for low to medium power applications, ensuring robust operation in various conditions.
Theoretical Analysis
SPWM (Sinusoidal Pulse Width Modulation) waves are PWM (Pulse Width Modulation) waves where the pulse width duty cycle varies sinusoidally. Proper filtering of these waves yields a sinusoidal output. Based on the voltage polarity of PWM waves, SPWM can operate in unipolar or bipolar modes. In bipolar SPWM inverter circuits, the two switches in the same bridge arm alternate between conduction and cutoff, whereas in unipolar SPWM, only one switch in a bridge arm conducts during each half-cycle, with the other remaining off. Unipolar SPWM exhibits one polarity during the positive half-cycle and the opposite during the negative half-cycle, resulting in reduced switching losses and higher efficiency compared to bipolar modulation.
The generation of SPWM waves involves comparing a sinusoidal modulation wave \( u_r \) with a triangular carrier wave \( u_c \). When the amplitude of \( u_r \) exceeds that of \( u_c \), switch S1 outputs a high level and S2 a low level; conversely, S1 outputs low and S2 high. During the positive half-cycle of \( u_r \), S3 remains low and S4 high, while during the negative half-cycle, S3 is high and S4 low. This modulation scheme ensures precise control of the inverter output. The switching signals S1 to S4 drive the gates of MOSFETs Q1 to Q4 in the full-bridge inverter circuit. In the positive half-cycle, Q1 performs high-frequency SPWM switching, Q4 remains continuously on, forming the main current path to the load, while Q2 provides a freewheeling path and Q3 stays off. In the negative half-cycle, Q2 switches based on SPWM, Q3 is continuously on, Q1 provides freewheeling, and Q4 remains off. This unipolar approach minimizes switching losses, making the single phase inverter more efficient.
The mathematical representation of SPWM modulation can be expressed as:
$$
\begin{cases}
\text{If } u_r > u_c, \quad S1 = \text{high}, S2 = \text{low} \\
\text{If } u_r < u_c, \quad S1 = \text{low}, S2 = \text{high}
\end{cases}
$$
Similarly, for the complementary switches:
$$
\begin{cases}
\text{If } u_r > 0, \quad S3 = \text{low}, S4 = \text{high} \\
\text{If } u_r < 0, \quad S3 = \text{high}, S4 = \text{low}
\end{cases}
$$
This ensures proper operation of the single phase inverter across both half-cycles.
Circuit Design
The system design comprises several key modules: an EG8010-based SPWM signal generation circuit, an IR2110S-based drive circuit, a full-bridge inverter circuit using IRF840 MOSFETs, an LC filter, a voltage feedback circuit, and protection circuits for overcurrent and overvoltage. Each module is critical to the performance of the single phase inverter.
Signal Generation Circuit
The EG8010 chip serves as the core SPWM wave generator. Key pins and their functions are summarized in Table 1. The chip operates with a 5V supply at pin 26 and a 5V reference at pin 17. Frequency selection pins FRQSEL0 and FRQSEL1 are set to “00” for 50Hz output. In unipolar modulation, pins 27 and 28 control the right bridge arm’s base wave output, while pins 29 and 30 provide SPWM modulation for the left bridge arm. Pin 13 (VFB) accepts voltage feedback for output stabilization, and pin 14 (IFB) handles load current feedback. This configuration ensures reliable generation of SPWM signals for the single phase inverter.
| Pin Number | Pin Name | Function Description |
|---|---|---|
| 26 | VCC | +5V power supply input |
| 3, 12 | GND | Ground pins |
| 6 | SPWMEN | SPWM output enable |
| 13 | VFB | Voltage feedback input |
| 14 | IFB | Load current feedback input |
| 17 | VREF | Internal reference voltage input |
| 18, 19 | FRQSEL0, FRQSEL1 | Frequency selection (“00” for 50Hz, “01” for 60Hz) |
| 27, 28 | SPWMOUT1, SPWMOUT2 | Right bridge arm SPWM outputs |
| 29, 30 | SPWMOUT3, SPWMOUT4 | Left bridge arm SPWM outputs |
Drive Circuit
Since the EG8010 output signals lack sufficient power to drive the MOSFETs directly, an IR2110S-based drive circuit is employed. Two IR2110S chips are used—one for each bridge arm. The left bridge arm drive circuit connects EG8010’s SPWMOUT3 and SPWMOUT4 to the HIN and LIN pins of an IR2110S, respectively. The HO and LO outputs drive the gates of Q1 and Q2 in the inverter circuit. A bootstrap circuit consisting of capacitor C5 and diode D1 provides a floating supply voltage for the high-side switch. Similarly, the right bridge arm uses another IR2110S driven by SPWMOUT1 and SPWMOUT2 to control Q3 and Q4. This design ensures fast and precise switching, essential for the single phase inverter’s efficiency.
Inverter Circuit
The full-bridge inverter is the core of the single phase inverter. It uses four IRF840 N-channel MOSFETs (Q1-Q4) arranged in a full-bridge configuration. During operation, when Q4 is on and Q3 off, Q1 and Q2 switch complementarily to produce the negative half-cycle; when Q3 is on and Q4 off, Q1 and Q2 switch to generate the positive half-cycle. Each MOSFET gate is protected with a series resistor (e.g., R1) and parallel diode (e.g., D2) to suppress voltage spikes, and a 10kΩ gate-source resistor (e.g., R2) prevents electrostatic accumulation and false triggering. The output of the full-bridge circuit is fed to an LC filter to produce a smooth sinusoidal waveform.
Filter Circuit
An LC filter is designed to attenuate harmonics and output a clean sine wave. Given the design specifications—output power \( P = 30 \, \text{W} \), output voltage \( U_o = 30 \, \text{V} \), frequency \( f = 50 \, \text{Hz} \), and cutoff frequency \( f_c = 300 \, \text{Hz} \)—the load resistance \( R \), inductance \( L \), and capacitance \( C \) are calculated as follows:
$$
R = \frac{U_o^2}{P} = \frac{30^2}{30} = 30 \, \Omega
$$
$$
L = \frac{R}{2 \pi f_c} = \frac{30}{2 \pi \times 300} \approx 16 \, \text{mH}
$$
$$
C = \frac{1}{2 \pi f_c R} = \frac{1}{2 \pi \times 300 \times 30} \approx 18 \, \mu\text{F}
$$
These values ensure effective filtering for the single phase inverter output.
Voltage Feedback Circuit
To maintain stable AC output voltage, a voltage feedback circuit is implemented. It consists of a voltage divider formed by resistors R9, R10, potentiometer R11, and capacitor C7. The sampled voltage is fed to the VFB pin of the EG8010, where it is compared with an internal reference. If the output voltage increases, the VFB voltage rises, and the internal circuit adjusts the SPWM to reduce the output, thus stabilizing it. Potentiometer R11 allows output voltage adjustment, and C7 filters high-frequency noise to prevent output instability. This feedback mechanism is vital for the reliability of the single phase inverter.
Protection Circuit
The protection circuit includes overvoltage and overcurrent protection using an LM324 op-amp and a 74LS02 NOR gate. For overvoltage protection, a voltage divider (R15, R16) provides a 2.5V reference to the LM324’s inverting input, while another divider (R12, R13, R14) samples the output voltage. If the sampled voltage exceeds 2.5V, the LM324 outputs high, which the NOR gate inverts to low, disabling the EG8010’s SPWMEN pin and halting SPWM generation. For overcurrent protection, the output current is sampled via resistors R19 and R20, amplified by the LM324, and compared to a 2.5V reference. If the current surpasses 1.2A, the comparator outputs high, triggering the NOR gate to disable the inverter. This dual protection ensures the single phase inverter safeguards against faults.
Test Results
Comprehensive testing was conducted to evaluate the performance of the single phase inverter. Key metrics included efficiency, load regulation, protection functionality, and long-term reliability.
Efficiency Test
With a fixed DC input voltage of 43V and current of approximately 0.8A, the output AC voltage and current were measured at 30V and 1A, respectively. Efficiency \( \eta \) was calculated as:
$$
P_I = I_I \times U_I, \quad P_O = I_O \times U_O, \quad \eta = \frac{P_O}{P_I} \times 100\%
$$
Multiple tests yielded the results in Table 2, showing an average efficiency of \( 87.83\% \pm 0.53\% \) for the single phase inverter.
| Input Voltage \( U_I \) (V) | Input Current \( I_I \) (A) | Output Voltage \( U_O \) (V) | Output Current \( I_O \) (A) | Efficiency \( \eta \) (%) |
|---|---|---|---|---|
| 43 | 0.82 | 30.08 | 1.03 | 87.59 |
| 43 | 0.75 | 29.87 | 0.95 | 87.26 |
| 43 | 0.78 | 29.91 | 0.99 | 88.14 |
| 43 | 0.84 | 30.15 | 1.07 | 88.36 |
Load Regulation Test
Load regulation was tested by varying the output current from 0.1A to 1.0A while keeping the input voltage constant. The load regulation \( S_I \) is given by:
$$
S_I = \left| \frac{U_O(0.1A) – U_O(1.0A)}{U_O} \right| \times 100\%
$$
where \( U_O(0.1A) \) and \( U_O(1.0A) \) are output voltages at 0.1A and 1.0A, respectively, and \( U_O = 30 \, \text{V} \). Results in Table 3 indicate a load regulation of \( 0.46\% \pm 0.04\% \), demonstrating the stability of the single phase inverter under varying loads.
| Input Voltage \( U_I \) (V) | \( U_O \) at 0.1A (V) | \( U_O \) at 1.0A (V) | Load Regulation \( S_I \) (%) |
|---|---|---|---|
| 36 | 30.13 | 30.28 | 0.50 |
| 36 | 29.92 | 30.06 | 0.48 |
| 36 | 29.93 | 30.07 | 0.46 |
| 36 | 29.90 | 30.03 | 0.45 |
| 36 | 29.91 | 30.04 | 0.43 |
Protection Circuit Test
The protection circuit was evaluated by monitoring the NOR gate output under overvoltage and overcurrent conditions. As shown in Table 4, when output voltage exceeded 32V or current surpassed 1.2A, the NOR gate output low (0V), disabling the SPWMEN pin and protecting the single phase inverter. Under normal conditions, the output remained high (3.822V), allowing continuous operation.
| Output Voltage (V) | Output Current (A) | NOR Gate Output (V) | NOR Gate Logic |
|---|---|---|---|
| 31.5 | 0.93 | 3.822 | 1 |
| 32.1 | 1.22 | 0.042 | 0 |
| 31.8 | 1.21 | 0.041 | 0 |
| 32.2 | 1.15 | 0.041 | 0 |
| 31.2 | 0.99 | 3.822 | 1 |
Anti-aging Test
Long-term reliability was assessed by operating the single phase inverter continuously for 96 hours with a DC input of 43V and 0.8A. Efficiency measurements at intervals (Table 5) revealed a gradual decline, with efficiency dropping by 3.15% after 96 hours, indicating acceptable aging characteristics for the single phase inverter design.
| Operating Time (H) | Input Voltage \( U_I \) (V) | Input Current \( I_I \) (A) | Output Voltage \( U_O \) (V) | Output Current \( I_O \) (A) | Efficiency \( \eta \) (%) |
|---|---|---|---|---|---|
| 24 | 43 | 0.8 | 30.05 | 1.00 | 87.64 |
| 48 | 43 | 0.8 | 29.87 | 0.99 | 86.19 |
| 72 | 43 | 0.8 | 29.64 | 0.99 | 85.32 |
| 96 | 43 | 0.8 | 29.53 | 0.98 | 84.49 |
Conclusion
This article detailed the design and implementation of a single phase inverter based on the EG8010 controller. The system integrates an EG8010-based SPWM generation module, IR2110S-driven full-bridge inverter, LC filter, voltage feedback, and protection circuits. Testing demonstrated that with a DC input of 43V, the single phase inverter achieves an output of 30V AC and 1A AC with an efficiency of \( 87.83\% \pm 0.53\% \) and load regulation of \( 0.46\% \pm 0.04\% \). The protection circuits reliably disable operation during faults, and long-term testing shows a moderate efficiency decline of 3.15% over 96 hours. Overall, the single phase inverter design meets performance requirements for renewable energy applications, offering a balance of efficiency, stability, and protection. Future work could focus on optimizing components for higher power levels and improved thermal management.