With the rapid development of renewable energy and advancements in power electronics, the application of inverters in modern power systems has become increasingly widespread. Inverters convert direct current (DC) power into stable alternating current (AC) power through periodic switching of power electronic devices, and they are widely used in household appliances, lighting, and electric tools. Traditional unipolar sinusoidal pulse width modulation (SPWM) output waveforms often suffer from high harmonic content and significant power loss. To address these issues, we designed a single-phase grid-connected inverter system based on bipolar SPWM. This system utilizes an STM32 microcontroller as the control core, leveraging its built-in high-precision timers to generate SPWM pulse signals. The IR2110 drive circuit produces four pulses to drive the full-bridge inverter circuit, controlling the switching states of the inverter. The inverted AC output is processed through an LC filter circuit to reduce harmonic content and improve the quality of the output AC power. The sampled AC signal is fed back to the microcontroller, and dual-loop control adjusts the SPWM pulses. Combined with synchronous phase-locking technology, this ensures that the inverter output accurately matches the grid voltage in frequency and phase, enhancing grid connection quality and efficiency. Experimental results demonstrate that the system can adjust the output frequency in the range of 2–200 Hz with a step of 1 Hz, maintain stable output voltage waveforms, and achieve excellent grid-connected current waveforms, validating the effectiveness of the design.
The overall system design of the single-phase grid-connected inverter is illustrated in the block diagram below. The circuit primarily consists of the STM32 main control circuit, IR2110 drive circuit, full-bridge inverter circuit, filter circuit, and sampling feedback circuit. The STM32 generates SPWM pulses, which are input into the drive circuit composed of two IR2110 chips. Each IR2110 drive circuit outputs two complementary PWM pulses, and the four pulses collaboratively drive the MOSFETs in the full-bridge circuit. In the full-bridge inverter circuit, the SPWM pulses act as chopping signals, producing high-voltage pulse waveforms. After processing by the LC low-pass filter, an AC sinusoidal power output is obtained. The inverter’s AC output port is connected to the load and the grid, with voltage and current sampling for feedback. The dual-loop controller adjusts the SPWM based on the feedback signals, while the STM32 performs synchronous phase-locking to generate a sinusoidal signal, enabling the conversion of DC power into AC power that is synchronized with the grid. Users can adjust the frequency via buttons, and the OLED display实时 shows input voltage, output amplitude, and frequency.
The main control module employs the STM32F103C8T6 microcontroller, which features a standard ARM architecture and a high-performance, low-cost, low-power Cortex-M3 core. This 32-bit microcontroller operates at up to 72 MHz, includes 64 KB of RAM, a 12-bit ADC, and a programmable prescaler TIMER module with input capture functionality, ensuring efficient inverter operation. The single-phase grid-connected inverter design focuses on reliability and efficiency, with the STM32 facilitating precise control of the SPWM generation.
The inverter circuit uses a single-phase full-bridge configuration as the main circuit. The operation principle relies on the switching of power transistors to convert DC input to AC output. The full-bridge inverter circuit comprises four bridge arms, each consisting of a controllable NMOS power switch and an anti-parallel diode for freewheeling. Diagonal bridge arms are driven by the same pulse, operating in a complementary manner. Specifically, when Q3 and Q5 are on and Q2 and Q4 are off, the voltage is U; when Q2 and Q4 are on and Q3 and Q5 are off, the voltage is -U. The four MOSFETs cycle to produce AC output. To protect the NMOS transistors, a resistor is series-connected at the gate, forming an RC charge-discharge circuit with the parasitic capacitance to limit gate current and prevent damage to the drive chip. The sinusoidal signal from the full-bridge inverter contains high-frequency components, necessitating a filter circuit. A 3 mH inductor and a 1 μF capacitor are selected for the LC filter, with the cutoff frequency calculated as:
$$ f_0 = \frac{1}{2\pi\sqrt{LC}} $$
where L is the inductance value and C is the capacitance value. This single-phase inverter design ensures minimal harmonic distortion and stable operation.
The drive circuit is constructed using two IR2110 chips, which are controlled via PWM signals. By adjusting the duty cycle of the PWM signals, the conduction time of the power switches is controlled, regulating the current through the load. The IR2110 operates at a voltage range of 10–20 V and integrates dual-channel high-voltage, high-speed gate drivers capable of independently driving high-side and low-side power switches. The high-side voltage is output from the HO1 and HO2 pins, driving the upper transistors of the left and right bridge arms in the full-bridge inverter circuit, while the LO1 and LO2 pins drive the lower transistors. The STM32’s I/O pin PB12 controls the output validity of the IR2110 drive circuit, with low level enabling output and high level disabling it. This configuration ensures efficient driving of the single-phase inverter switches.
The output sampling circuit for the single-phase inverter includes voltage and current feedback. The voltage sampling circuit converts the inverted AC voltage into a small AC signal via a voltage transformer, then uses a two-stage operational amplifier to convert it into a voltage sampling signal within the 0–3.3 V range required for ADC conversion. The sampled signal is input to the STM32 through pin PB4. A potentiometer PR1 adjusts the signal amplitude, and diodes D1 and D2 form a limiter circuit to protect the ADC input. Similarly, the current sampling circuit inputs the signal to the STM32 via pin PB5. This feedback mechanism is crucial for the dual-loop control in the single-phase grid-connected inverter.
For power supply design, a low-cost, practical linear regulated power supply is implemented using the AMS1117 voltage regulator chip, which outputs 5 V and 3.3 V to power the system. The AMS1117 can handle input voltages up to 18 V, and in this design, it is supplied with 12 V. The display module uses a common 128×64 resolution OLED screen, and the key module comprises four buttons for adjusting the output frequency and amplitude of the single-phase inverter, detected via low-level active mode.
Inverter grid connection control addresses fluctuations in output voltage and current due to load characteristics and grid conditions, which can cause waveform distortion and synchronization issues. The single-phase grid-connected inverter employs dual-loop control with voltage outer loop and current inner loop, using a current control strategy. The control block diagram illustrates the process: the voltage outer loop compares the reference voltage Vref with the actual DC voltage feedback Vfb, and after PI control, outputs the current reference Iref. This is multiplied by a sinusoidal reference signal generated from the grid voltage phase θgrid and frequency fgrid obtained by the phase-locked loop (PLL). The current inner loop compares Iref with the actual current feedback Ifb and adjusts the SPWM pulses via a PR controller. The transfer functions for the voltage outer loop GV(s) and current inner loop GI(s) are critical for stability.
The current inner loop uses a quasi-PR controller, which introduces a resonant环节 at the grid frequency to achieve infinite gain for the fundamental frequency signal, enabling zero steady-state error tracking. The ideal PR controller transfer function is:
$$ G_I(s) = K_p + \frac{K_r s}{s^2 + \omega_0^2} $$
where Kp is the proportional gain, Kr is the resonant gain, and ω0 is the resonant angular frequency. For an input signal M sin(ωt + φ), the time-domain response after the resonant环节 is derived to show phase synchronization and error reduction. Considering bandwidth ωc, the PR controller transfer function becomes:
$$ G_I(s) = K_p + \frac{K_r \omega_c s}{s^2 + 2\omega_c s + \omega_0^2} $$
where ωc is the cutoff frequency and ω0 is the fundamental frequency. The current error eI(t) = Iref(t) – Ifb(t) is processed by the PR controller to produce the control signal for bipolar SPWM:
$$ u(t) = G_I(s) \cdot e_I(t) = \left[ K_p + \frac{K_r \omega_c s}{s^2 + 2\omega_c s + \omega_0^2} \right] \cdot e_I(t) $$
The voltage outer loop employs a PI controller to stabilize the DC bus voltage, with the transfer function:
$$ G_V(s) = K_p + \frac{K_{iv}}{s} $$
where Kp is the proportional gain and Kiv is the integral gain. The integral eliminates steady-state error, and the proportional term speeds up response. The voltage error eV(t) = Vref(t) – Vfb(t) yields the output control signal for the current reference:
$$ I_{\text{ref}}(t) = K_p e_V(t) + K_{iv} \int_0^t e_V(\tau) d\tau $$
Parameters for the dual-loop controller are designed based on experimental analysis of amplitude-frequency and phase-frequency characteristics, with ω0 = 314 rad/s, resulting in current inner loop parameters Kp = 0.1, Kr = 30, ωc = 10, and voltage outer loop parameters Kp = 5, Kiv = 50. This ensures robust performance of the single-phase inverter under varying conditions.
The software design for the single-phase grid-connected inverter begins with main program initialization. The flow involves defining functions and variables, initializing GPIO, interrupt priority, keys, ADC, timers, and OLED display. The main loop continuously monitors and responds to external inputs, using keys and serial commands to adjust output voltage and frequency in real-time. Over-voltage and over-current protection is implemented; if thresholds are exceeded, output is cut off, otherwise sampling continues. If voltage fluctuates, SPWM parameters are recalculated. Key operations delay display updates by 3 seconds. This structure ensures reliable operation of the single-phase inverter.
The bipolar SPWM algorithm is implemented using the STM32F103’s high-frequency input clock up to 72 MHz. The TIMX timer controls I/O output of PWM pulses. TIM1, an advanced timer, generates up to 7 PWM outputs, meeting the design’s requirement for 4 SPWM channels, with complementary output and dead-time settings. TIM1 allows setting auto-reload values and initial levels for each PWM. The counter TIM1 → CCRn controls waveform flipping for each complementary PWM, enabling flexible pulse width adjustment and duty cycle control. To prevent short-circuit breakdown from simultaneous conduction of MOSFETs in the full-bridge inverter, timers TIM2 and TIM3 are set to up-counting mode with PWM1 mode, initial values, and dead time (set via UTG[7:0] bits). In PWM mode, the timer produces a signal with frequency determined by the auto-reload register TIMX_ARR and duty cycle by the capture/compare register TIMX_CCR. In this design, TIMX_ARR is written with the frequency value for sinusoidal inversion, and TIMX_CCR with SPWM array data. When the timer overflows and interrupts, indicating the end of a switching period, the next SPWM data is written to TIMX_CCR,循环 generating SPWM signals. The program flow for STM32 SPWM generation ensures precise control for the single-phase inverter.
The interrupt subroutine handles real-time control of the single-phase inverter. Timer TIM1 interrupts at 20 kHz, reading the inverter’s output voltage and current values, adjusting SPWM pulses, and activating current protection. If no over-voltage or over-current occurs, the system reads grid voltage values. For grid connection, a PLL locks the grid voltage phase, and the synchronized phase and frequency generate a sinusoidal signal that, combined with dual-loop control, adjusts SPWM pulses. By updating the duty cycle, the output is regulated to ensure synchronization with the grid. Finally, A/D conversion is started to prepare for the next voltage and current reading. After the flow, the system returns, awaiting the next interrupt event, maintaining efficient operation of the single-phase grid-connected inverter.
System testing involved building hardware based on the circuit design, compiling with Keil5, setting the switching frequency to 20 kHz, and inputting 12 V DC. The output frequency is adjustable from 2 to 200 Hz with a 1 Hz step. The filtered AC output voltage waveform shows a nearly ideal sinusoidal shape, smooth and without significant spikes or distortion, indicating stable inversion. The table below analyzes the output frequency regulation results, verifying inverter output frequency stability. In the 50–100 Hz range, the error is within ±0.5 Hz, with error increasing slightly as the set frequency rises. The grid-connected output frequency is 50 Hz, meeting error requirements.
| Set Frequency (Hz) | Output Frequency (Hz) | Error (Hz) | Error Accuracy Ratio (%) |
|---|---|---|---|
| 50 | 49.95 | -0.05 | -0.10 |
| 55 | 54.91 | -0.09 | -0.16 |
| 60 | 59.87 | -0.13 | -0.22 |
| 65 | 64.82 | -0.18 | -0.28 |
| 70 | 69.79 | -0.21 | -0.30 |
| 75 | 74.72 | -0.28 | -0.37 |
| 80 | 79.68 | -0.32 | -0.40 |
| 85 | 84.64 | -0.36 | -0.42 |
| 90 | 89.58 | -0.42 | -0.47 |
| 95 | 94.55 | -0.45 | -0.47 |
| 100 | 99.51 | -0.49 | -0.49 |
The grid-connected output voltage and current waveforms demonstrate synchronization with the grid voltage in frequency and phase, maintaining stability during operation. This further validates the frequency tracking and synchronization capabilities of the dual-loop controlled bipolar SPWM single-phase grid-connected inverter. The design achieves low harmonic content, efficient operation, and reliable grid integration.
In conclusion, we have designed and implemented a low-power single-phase grid-connected inverter. The system uses an STM32 as the main control core, a full-bridge inverter as the main circuit, and employs dual-loop control with bipolar SPWM modulation combined with PLL technology to control the single-phase inverter output for sinusoidal AC power synchronized with the grid. Experimental results show that the inverter output frequency is adjustable with small errors, the dual-loop control algorithm ensures stable output voltage and current waveforms with low harmonic content, and grid connection achieves rapid synchronization with minimal phase and frequency differences. This design offers advantages such as simple circuitry, low cost, and low power consumption, providing a feasible solution for single-phase grid-connected inverter applications. The single-phase inverter proves to be a reliable and efficient component in modern power systems, supporting the integration of renewable energy sources.