In modern power electronics, the single phase inverter plays a critical role in applications such as uninterruptible power supplies (UPS), renewable energy integration, and motor drives. The performance of a single phase inverter is largely determined by its control strategy, which must ensure high-quality output voltage with minimal distortion and robust dynamic response. Traditional control approaches, including proportional-integral (PI) and repetitive control, have limitations in tracking AC signals and suppressing DC bias, which can adversely affect transformer-coupled loads. In this work, we propose an enhanced dual-loop control scheme for a single phase inverter, incorporating a proportional controller in the inner current loop and a quasi-proportional-integral-resonant (PIR) controller in the outer voltage loop. Additionally, we design a DC bias detection circuit and a dedicated suppression loop to mitigate the detrimental effects of DC offset. This article details the mathematical modeling, controller design, stability analysis, and experimental validation of the proposed method, demonstrating its effectiveness in improving the performance of single phase inverters.
The fundamental topology of a single phase inverter consists of a half-bridge configuration with IGBT switches and an LC filter, as illustrated in the following figure. This structure is common in three-phase UPS systems, where each phase operates independently, allowing analysis on a per-phase basis. The output voltage quality of a single phase inverter is influenced by parasitic resistances, switching dead times, and asymmetries in DC bus components, which can introduce DC bias. This bias, if unaddressed, can cause saturation in transformers and increased losses, underscoring the need for advanced control techniques.
To establish a foundation for control design, we derive the mathematical model of the single phase inverter in the frequency domain. The Kirchhoff’s Current Law (KCL) at the load node yields:
$$ i_L(s) = u_o(s) C s + i_o(s) $$
where \( i_L(s) \), \( u_o(s) \), and \( i_o(s) \) represent the inductor current, output voltage, and load current in the Laplace domain, respectively. Applying Kirchhoff’s Voltage Law (KVL) to the circuit loop gives:
$$ u_{ao}(s) = u_o(s) + i_L(s) (r + L s) $$
Here, \( u_{ao}(s) \) is the inverter output voltage, \( L \) is the filter inductance, \( C \) is the filter capacitance, and \( r \) is the equivalent series resistance. For sinusoidal pulse-width modulation (SPWM) with bipolar switching, the relationship between the modulation signal \( u_c(s) \) and the inverter output is:
$$ \frac{u_c(s)}{U_{tri}} = \frac{u_{ao}(s)}{U_{dc}} $$
where \( U_{tri} \) is the peak triangular carrier voltage and \( U_{dc} \) is the DC bus voltage. Combining these equations, the transfer function from the modulation signal to the output voltage, with load current as a disturbance, is derived as:
$$ G(s) = \frac{u_o(s)}{u_c(s)} = \frac{U_{dc}}{U_{tri}} \cdot \frac{1}{L C s^2 + (r C) s + 1} $$
This model forms the basis for designing the control loops, ensuring that the single phase inverter operates efficiently under varying loads.
The dual-loop control strategy employs an inner current loop and an outer voltage loop. The inner loop uses a proportional controller to dampen system resonances and improve stability, while the outer loop utilizes a quasi-PIR controller to achieve zero steady-state error for AC signals and suppress DC components. The overall control block diagram includes delay elements \( G_d(s) = e^{-T_d s} \), where \( T_d = 1.5 T_s \) accounts for computational and PWM delays, and \( T_s \) is the switching period. The quasi-PIR controller transfer function is defined as:
$$ G_{PIR}(s) = k_p + \frac{k_i}{s} + \frac{k_r \omega_c s}{s^2 + 2 \omega_c s + \omega_0^2} $$
where \( k_p \), \( k_i \), and \( k_r \) are the proportional, integral, and resonant gains, respectively, \( \omega_c \) is the cutoff frequency, and \( \omega_0 \) is the resonant frequency set to the fundamental output frequency (e.g., 100π rad/s for 50 Hz).
For the inner current loop, the proportional controller \( k_c \) is designed to act as a virtual impedance, enhancing damping. The closed-loop transfer function from the current reference to the output voltage is:
$$ G_C(s) = \frac{k_c G_d(s)}{L C s^2 + (r C + k_c C) s + 1} $$
The damping ratio \( \zeta \) is given by:
$$ \zeta = \frac{(r + k_c)}{2} \sqrt{\frac{C}{L}} $$
To ensure stability, the phase margin (PM) and gain margin (GM) must be positive. The phase margin is calculated as:
$$ \text{PM} = 180^\circ + \arctan\left( \frac{(r + k_c) C \omega_g}{L C \omega_g^2 – 1} \right) $$
where \( \omega_g \) is the gain crossover frequency. The gain margin is:
$$ \text{GM} = 20 \log_{10} \left| \frac{k_c}{\sqrt{(r + k_c)^2 \omega_p^2 + (1 – L C \omega_p^2)^2}} \right| $$
with \( \omega_p \) being the phase crossover frequency. To avoid negative virtual impedance effects, \( \omega_g \) is constrained to less than \( \frac{1}{6 T_s} \). For a 10 kW single phase inverter with parameters \( L = 1.2 \, \text{mH} \), \( C = 80 \, \mu\text{F} \), \( r = 0.2 \, \Omega \), and \( f_s = 10 \, \text{kHz} \), selecting \( f_g = 1.5 \, \text{kHz} \) yields \( k_c = 0.8 \). The resulting PM is 55°, indicating stable operation.
The voltage outer loop design involves tuning the quasi-PIR controller parameters. The open-loop transfer function is:
$$ G_U(s) = G_C(s) G_{PIR}(s) G_d(s) $$
The proportional gain \( k_p \) determines the bandwidth, set to 400 Hz for a balance between dynamic response and noise immunity, resulting in \( k_p = 1.2 \). The integral gain \( k_i \) is chosen to be 150 to maintain a PM over 60°, and the resonant gain \( k_r = 98 \) ensures less than 0.5% steady-state error at 50 Hz. The cutoff frequency \( \omega_c \) is set to 4 rad/s for frequency adaptability. The stability of the voltage loop is verified with a PM of 50° and a bandwidth of 500 Hz.
Despite the dual-loop control, DC bias in the single phase inverter output persists due to asymmetries in IGBT characteristics, dead-time effects, and DC bus imbalances. This bias, though small, can be detrimental in transformer-coupled loads. The voltage sampling circuit, typically using a 12-bit ADC, has a resolution limit. For a 220 V RMS output, the peak voltage is 311 V, and with a 1.15 safety margin, the maximum sampling voltage is 715 V. The ADC resolution \( \varepsilon \) is:
$$ \varepsilon = \frac{U_{AD}}{2^n} = \frac{715}{4096} \approx 0.175 \, \text{V} $$
Thus, DC components below this threshold are not suppressed by the control loop. To address this, we introduce a DC bias detection circuit and an additional suppression loop.
The DC bias detection circuit is a low-pass filter designed to attenuate the fundamental AC component while passing DC signals. It consists of a differential attenuation stage, an inverting stage, and a bias stage. The transfer function is:
$$ H_U(s) = \frac{v_o(s)}{v_{in}(s)} = \frac{1}{b_1 s^3 + b_2 s^2 + b_3 s + 1} $$
where \( b_1 = R_4 R_7 R_9 C_1 C_3 C_5 \), \( b_2 = R_4 R_9 C_1 C_5 + R_7 R_9 C_3 C_5 + R_4 R_7 R_9 C_1 C_3 \), and \( b_3 = R_4 C_1 + R_7 C_3 + R_9 C_5 \). With component values \( R_1 = R_2 = R_3 = R_4 = 500 \, \text{k}\Omega \), \( R_5 = R_7 = R_8 = 1 \, \text{M}\Omega \), \( R_9 = 1 \, \text{k}\Omega \), \( C_1 = C_2 = C_3 = C_4 = 1 \, \mu\text{F} \), and \( C_5 = C_6 = 0.1 \, \mu\text{F} \), the circuit attenuates the 50 Hz component by 90 dB, effectively isolating the DC bias.
The improved control scheme incorporates a DC suppression loop, where the detected DC bias \( u_{dc} \) is compared to zero and processed by a PI controller \( G_{dc}(s) = k_{dcP} + \frac{k_{dcI}}{s} \). The output is added to the voltage reference, forming a composite control signal. The open-loop transfer function of the DC suppression loop is approximated as:
$$ H_{dc}(s) = H_U(s) G_{dc}(s) $$
assuming the voltage loop gain is unity at DC. Setting the bandwidth to 1 Hz and the PI corner frequency to 0.1 Hz, we obtain \( k_{dcP} = 3.9 \) and \( k_{dcI} = 2.4 \). The PM for this loop is 55°, ensuring stability.
To validate the proposed method, simulations and experiments are conducted on a 10 kW single phase inverter system. The system parameters are summarized in Table 1.
| Parameter | Value |
|---|---|
| Rated Power | 10 kW |
| Grid Voltage (RMS) | 220 V |
| DC Voltage \( U_{dc} \) | 720 V |
| Output Voltage (RMS) | 220 V |
| Switching Frequency \( f_s \) | 10 kHz |
| Output Frequency \( f_0 \) | 50 Hz |
| Filter Inductance \( L \) | 1.2 mH |
| Filter Capacitance \( C \) | 80 μF |
| Equivalent Resistance \( r \) | 0.2 Ω |
| Current Controller Gain \( k_c \) | 0.8 |
| Voltage Controller Gains \( k_p, k_i, k_r \) | 1.2, 150, 98 |
| DC Suppression Gains \( k_{dcP}, k_{dcI} \) | 3.9, 2.4 |
Simulation results under no-load and full-load conditions show that the output voltage total harmonic distortion (THD) is below 1.5%. Without DC suppression, the output DC bias is -400 mV, but with the proposed loop, it is reduced to nearly zero. Dynamic performance during load transitions exhibits less than 2% overshoot and a settling time under 15 ms. The DC suppression loop effectively eliminates bias without compromising dynamic response.
Experimental results on a hardware platform with a TMS320F2812 DSP controller confirm the simulations. The output voltage THD is below 1.2% with high precision. The DC bias is reduced from -200 mV to within 30 mV, demonstrating the efficacy of the approach. The single phase inverter maintains stability and performance across various operating conditions.
In conclusion, the improved dual-loop control strategy with DC bias suppression significantly enhances the performance of single phase inverters. The proportional current controller and quasi-PIR voltage controller ensure robust tracking and stability, while the dedicated DC suppression loop mitigates bias effects. This method is particularly beneficial for applications requiring high power quality, such as UPS and renewable energy systems. Future work could explore adaptive tuning and integration with grid-support functions.