In the context of global energy scarcity, promoting green and low-carbon development and accelerating ecological civilization construction are essential to fundamentally address energy shortages. Solar power generation, as a clean and renewable energy source, represents an effective measure to combat energy scarcity in many regions and holds promising development prospects. Grid integration requires solar inverters to achieve energy conversion, and the performance of these solar inverters directly impacts energy utilization efficiency. Multilevel solar inverters have become a research hotspot due to their advantages, such as high boost capability, low total voltage stress, low total harmonic distortion (THD) in multilevel voltage output, reduced weight and volume of filters, and the ability to generate multiple voltage levels. However, traditional multilevel solar inverters often suffer from complex structures and excessive power devices, leading to higher costs and lower efficiency. To address these issues, we investigate widely used switched-capacitor solar inverters and propose an expanded switched-capacitor multilevel solar inverter topology. The proposed solar inverter topology features fewer total devices, a simpler structure, lower cost, reduced total voltage stress, and self-balancing capacitor voltage performance. Compared to conventional multilevel solar inverters, this topology offers four times boost capability and multi-level voltage output, requiring only simple control for grid connection, thereby saving costs. Furthermore, the innovative topology is expandable; by adding a small number of components, it can achieve a seventeen-level output with a maximum eight-fold boost capability. Experimental results validate the superiority of the proposed switched-capacitor solar inverter topology.
The proposed solar inverter topology is designed to overcome the limitations of traditional multilevel solar inverters, such as structural complexity and high power loss. It consists of a front-end switched-capacitor circuit and a rear-end full-bridge circuit. The front-end circuit includes a DC input voltage source \( U_{dc} \), capacitors \( C_1 \) and \( C_2 \), switches \( S_5 \) to \( S_9 \), and two diodes. Through series and parallel combinations of the capacitors and DC source, this section generates four positive polarity step waves: \( 4U_{dc} \), \( 3U_{dc} \), \( 2U_{dc} \), and \( U_{dc} \). The rear-end full-bridge circuit, composed of switches \( S_1 \) to \( S_4 \), facilitates polarity reversal and can short-circuit to output zero voltage. Overall, the solar inverter requires one DC source, two capacitors, nine switches, and two diodes to produce nine output levels: \( \pm 4U_{dc} \), \( \pm 3U_{dc} \), \( \pm 2U_{dc} \), \( \pm U_{dc} \), and 0. This simplification enhances efficiency and reduces costs compared to existing solar inverter structures.
The operating principles of the solar inverter are analyzed over one power frequency cycle, during which it outputs nine distinct working states. The key operational modes are summarized in Table 1, where “1” indicates a switch is on, “0” indicates off, “C” denotes capacitor charging, “D” denotes discharging, and “-” indicates a floating state. For analysis, we assume capacitors have sufficient capacitance to ignore voltage fluctuations, all active devices have zero resistance when on, and the circuit is in a steady state. In Mode 1 (\( \pm 4U_{dc} \)), switches \( S_1 \), \( S_4 \), \( S_6 \), and \( S_7 \) are on. For resistive load with positive current, the current path involves the DC source \( U_{dc} \), capacitors \( C_1 \) and \( C_2 \), and switches \( S_6 \) and \( S_7 \), outputting \( 4U_{dc} \). For negative current, the output remains \( 4U_{dc} \). In Mode 2 (\( \pm 3U_{dc} \)), switches \( S_1 \), \( S_4 \), \( S_6 \), \( S_8 \), and diode \( D_1 \) are on. Positive current results in \( U_{dc} \) charging \( C_1 \) in parallel while \( C_2 \) discharges in series, outputting \( 3U_{dc} \). Mode 3 (\( \pm 2U_{dc} \)) involves switches \( S_1 \), \( S_4 \), \( S_5 \), \( S_7 \), \( S_9 \), and diode \( D_2 \) on, where \( U_{dc} \) and \( C_1 \) charge \( C_2 \) in parallel, outputting \( 2U_{dc} \). Mode 4 (\( \pm U_{dc} \)) has switches \( S_1 \), \( S_4 \), \( S_5 \), and \( S_8 \) on, with capacitors floating and outputting \( U_{dc} \). Mode 5 (0) occurs when switches \( S_6 \) and \( S_9 \) are off, outputting zero voltage. These modes demonstrate the solar inverter’s ability to efficiently generate multiple voltage levels with self-balancing capacitors, a key advantage for solar inverter applications.
| Output Level | S1 | S2 | S3 | S4 | S5 | S6 | S7 | S8 | S9 | D1 | D2 | C1 | C2 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 4Udc | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | D | D |
| 3Udc | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | C | D |
| 2Udc | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | D | C |
| Udc | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | C | – |
| 0+ | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | – | – |
| 0- | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | – | – |
| -Udc | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | C | – |
| -2Udc | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | D | C |
| -3Udc | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | C | D |
| -4Udc | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | D | D |
To enhance output voltage and increase the number of output levels, the proposed solar inverter topology is expandable. Each additional level requires only four switches and one capacitor. For \( n \) capacitors, the output level number is \( 2^{n+1} + 1 \), achieving a boost gain of \( 2^{n+1} + 1 \), with the number of switches required being \( 4n + 3 \). This design allows the number of components to increase linearly while the output voltage levels and level count increase exponentially, significantly improving device utilization. For instance, expanding to a seventeen-level solar inverter involves adding one capacitor and four switches, resulting in a structure that can output up to seventeen levels with an eight-fold boost. The expanded solar inverter maintains self-balancing capacitor voltages, with capacitors \( C_1 \), \( C_2 \), and \( C_3 \) stabilizing at \( U_{dc} \), \( 2U_{dc} \), and \( 4U_{dc} \), respectively, through series and parallel charging and discharging without additional control strategies. This expandability makes the solar inverter highly versatile for various applications, including high-power solar inverter systems.
The modulation strategy for the solar inverter employs in-phase carrier pulse width modulation (PWM) to simplify control and reduce harmonics. This method uses four triangular carriers with amplitude \( A_c \) and frequency \( f_c \), layered continuously along the horizontal axis. A sinusoidal reference wave with amplitude \( A \) and frequency \( f \) is compared to these carriers to generate five original PWM pulses, labeled \( g_0 \) to \( g_5 \). The modulation index \( M_a \) is defined as:
$$ M_a = \frac{A}{4A_c} $$
We set the modulation index to 0.9 for optimal performance. The drive signals for the nine switches are derived from logical combinations of the comparison results, as shown in the equations below. For example, the drive signal \( u_1 \) for switch \( S_1 \) is given by \( u_1 = \pm (g_0 + g_1 + g_2 + g_3 + g_4) \), where “±” indicates polarity based on the half-cycle. Similarly, other drive signals are computed as follows:
$$ u_2 = \pm (g_0 – g_1 – g_2 – g_3 – g_4) $$
$$ u_4 = g_1 + g_2 + g_3 + g_4 $$
$$ u_5 = \pm g_0 \pm g_1 \pm g_2 $$
$$ u_6 = g_3 + g_4 $$
$$ u_7 = \pm g_0 \pm g_2 \pm g_4 $$
$$ u_8 = \pm g_1 \pm g_3 $$
$$ u_9 = \pm g_0 \pm g_2 $$
This PWM strategy ensures efficient switching and minimizes THD, making it suitable for solar inverter applications. The solar inverter’s capacitor voltages self-balance without additional control, as seen in the operational modes where capacitors charge and discharge alternately. For instance, at output voltage \( U_{dc} \), capacitor \( C_1 \) charges while \( C_2 \) floats; at \( 2U_{dc} \), \( C_1 \) discharges and charges \( C_2 \); at \( 3U_{dc} \), \( C_1 \) charges while \( C_2 \) discharges; and at \( 4U_{dc} \), both capacitors discharge. This inherent balance simplifies the solar inverter design and enhances reliability.
Capacitor parameter design is crucial for minimizing voltage ripple, which affects output waveform quality and power loss. The voltage ripple \( \Delta U_C \) is calculated based on the discharge quantity \( \Delta Q_C \) over a time interval \( t_a \) to \( t_b \):
$$ \Delta Q_C = \int_{t_a}^{t_b} I_o \sin(2\pi f t – \phi) \, dt $$
where \( I_o \) is the output current amplitude, \( f \) is the load current frequency, and \( \phi \) is the phase difference between output voltage and load current for inductive loads. The voltage ripple is then:
$$ \Delta U_C = \frac{\Delta Q_C}{C} $$
To ensure low ripple, capacitor values are selected such that \( C \geq \frac{Q}{\Delta U} \), where \( \Delta U \) is the maximum allowable ripple (e.g., 10% for \( C_2 \) and 5% for \( C_1 \)). For the nine-level solar inverter, we chose \( C_1 = 6800 \, \mu\text{F} \) and \( C_2 = 4700 \, \mu\text{F} \), with rated voltages of 50 V and 100 V, respectively. For the expanded seventeen-level solar inverter, an additional capacitor \( C_3 = 2200 \, \mu\text{F} \) with a rated voltage of 200 V is used. These values ensure stable operation and minimal ripple in solar inverter systems.
Loss analysis in the solar inverter considers three types of power losses: switching losses \( P_S \), conduction losses \( P_C \), and losses due to capacitor voltage ripple \( P_R \). Switching losses occur during transition times \( t_{\text{on}} \) and \( t_{\text{off}} \), and are calculated for each switch as:
$$ P_{S,\text{ON}} = \frac{1}{6} f_S U_S I_S t_{\text{on}} $$
$$ P_{S,\text{OFF}} = \frac{1}{6} f_S U_S I_S t_{\text{off}} $$
where \( f_S \) is the switching frequency, \( U_S \) is the off-state voltage, and \( I_S \) is the on-state current. Total switching loss is the sum over all switches. Conduction losses arise from parasitic resistances of switches \( r_s \), diodes \( r_D \), and capacitors \( r_C \). The equivalent parasitic resistance for each output level is listed in Table 2. For example, at output levels between 0 and \( U_{dc} \), the resistance is \( 4r_D + 2r_s \). Energy loss \( E \) over a time interval is integrated based on current paths, and total conduction loss \( P_C \) is derived from these energies multiplied by the reference frequency. Capacitor ripple losses \( P_R \) are computed as \( P_R = f_{\text{ref}} C (\Delta U_{\text{ripple}})^2 \). Overall, the solar inverter exhibits high efficiency, exceeding 94% over a wide power range up to 2.5 kW, with a peak efficiency of 98.77% under optimized parameters.
| Output Voltage | Parasitic Resistance |
|---|---|
| 0 | 4r_D + 2r_s |
| ±Udc | 2r_D + 2r_s |
| ±2Udc | r_D + 3r_s + r_C |
| ±3Udc | r_D + 3r_s + r_C |
| ±4Udc | 4r_s + 2r_C |
A comparative analysis with other nine-level and seventeen-level solar inverters highlights the advantages of the proposed topology. For nine-level solar inverters, as shown in Table 3, our design uses fewer components (9 switches, 2 diodes, 2 capacitors) and has a lower total standing voltage (TSV) of 25 times the step voltage \( U_{\text{step}} \), compared to alternatives. The cost function (CF), which accounts for component count and TSV, is 47 for our solar inverter, indicating superior cost-effectiveness. The boost gain is 4, matching or exceeding other topologies. For seventeen-level solar inverters, Table 4 demonstrates that our solar inverter requires only 15 switches and 3 capacitors, with a TSV of 42 times \( U_{\text{step}} \) and a peak inverse voltage (PIV) of 8 times the input voltage \( E \). This represents a significant reduction in components and voltage stress compared to existing solar inverters, making it ideal for high-efficiency solar applications.
| Reference | Nswitch | Ndriver | Ndiode | Ncap | TSV (×Ustep) | CF | Gain |
|---|---|---|---|---|---|---|---|
| [12] | 9 | 8 | 2 | 2 | 30 | 51 | 2 |
| [13] | 10 | 10 | 3 | 2 | 25 | 50 | 4 |
| [14] | 8 | 8 | 3 | 3 | 26 | 48 | 4 |
| [15] | 10 | 8 | 6 | 3 | 28 | 55 | 4 |
| Proposed | 9 | 9 | 2 | 2 | 25 | 47 | 4 |
| Reference | Ns | Ncap | TSV (×Ustep) | PIV | Gain |
|---|---|---|---|---|---|
| [16] | 26 | 7 | 95 | 8E | 8 |
| [17] | 24 | 8 | 53 | 8E | 8 |
| [18] | 20 | 5 | 52 | 8E | 8 |
| [19] | 19 | 4 | 53 | 6E | 6 |
| Proposed | 15 | 3 | 42 | 8E | 8 |
Experimental validation of the nine-level and seventeen-level solar inverters was conducted under resistive load conditions with varying modulation indices. For the nine-level solar inverter, parameters included a DC input voltage of 30 V, capacitors \( C_1 = 6800 \, \mu\text{F} \) and \( C_2 = 4700 \, \mu\text{F} \), load resistance of 100 Ω, carrier frequency of 10 kHz, and modulation indices of 0.9, 0.6, 0.4, and 0.2. The output levels correspond to the modulation index as follows: 9 levels for \( 0.75 < M_a \leq 1 \), 7 levels for \( 0.5 < M_a \leq 0.75 \), 5 levels for \( 0.25 < M_a \leq 0.5 \), and 3 levels for \( 0 < M_a \leq 0.25 \). Experiments showed smooth transitions between levels when the modulation index changed every 40 ms, with filtered voltage and current waveforms maintaining sinusoidal shapes. Capacitor voltages \( U_{C1} \) and \( U_{C2} \) stabilized at approximately 30 V and 60 V, respectively, confirming self-balancing without additional control. For the seventeen-level solar inverter, parameters included a DC input of 10 V, capacitors \( C_1 = 6800 \, \mu\text{F} \), \( C_2 = 4700 \, \mu\text{F} \), \( C_3 = 2200 \, \mu\text{F} \), load resistance of 100 Ω, output frequency of 50 Hz, carrier frequency of 10 kHz, and modulation indices of 0.9, 0.8, 0.7, and 0.6. Results demonstrated output levels up to seventeen with an eight-fold boost, and capacitor voltages \( U_{C1} \), \( U_{C2} \), and \( U_{C3} \) balanced at 10 V, 20 V, and 40 V, respectively, with ripples below 5 V. These experiments verify the feasibility and superiority of the proposed solar inverter topology for practical applications.
In conclusion, we have proposed a single-input expandable switched-capacitor multilevel solar inverter topology that addresses the limitations of traditional solar inverters. The solar inverter offers multiple voltage levels, low voltage stress, high boost capability, cost-effectiveness, high efficiency, and self-balancing capacitors. Through detailed analysis of topology, modulation, capacitance, losses, and comparisons, along with experimental validation, we have demonstrated its effectiveness. The solar inverter’s ability to switch between different voltage levels based on modulation index and its expandability to seventeen levels make it a versatile solution for solar energy systems. Future work could focus on optimizing the solar inverter for higher power applications and integrating advanced control strategies for enhanced grid compatibility.