As human society continues to advance, the demand for energy and environmental protection has become increasingly intense. The development and utilization of renewable energy sources have gradually entered the public spotlight, and solar energy, as a sustainable and clean energy source, holds a pivotal position in the development and utilization of renewable energy. Among solar energy applications, photovoltaic (PV) power generation is one of the most important fields. The photovoltaic inverter, serving as the link between the solar panels and the grid, plays a crucial role in improving the efficiency of solar energy utilization. With technological progress, the existing photovoltaic inverter topologies have evolved to the stage of non-isolated photovoltaic inverters. Compared with conventional isolated inverters, the removal of the transformer has significantly reduced the weight, volume, and cost while improving the efficiency. However, because of the lack of galvanic isolation, the high-frequency common-mode voltage generated by the inverter acts on the parasitic capacitance between the photovoltaic panels, the ground, and the utility grid, forming a path for leakage current. Leakage current not only degrades the output quality of the inverter but also, when exceeding a certain level, can threaten the safety of electrical equipment and personnel. Therefore, the suppression of leakage current in non-isolated photovoltaic inverters has become an increasingly important research topic.
In this work, I present a comprehensive study on a novel eleven-switch clamped three-phase photovoltaic inverter topology for leakage current suppression. The proposed topology builds upon the conventional three-phase inverter by adding a freewheeling circuit and a clamping circuit. The freewheeling circuit provides a continuous current path without passing through the relatively poor diodes inside the switching devices, and it also disconnects the DC side from the AC side during the freewheeling mode, establishing an independent freewheeling path. The clamping circuit clamps the common-mode voltage to half of the DC bus voltage during the freewheeling interval. With the proposed control method, the common-mode voltage is kept varying between one-third and two-thirds of the bus voltage, thereby reducing the common-mode voltage variation range and effectively suppressing the leakage current. I have carried out detailed theoretical analysis, simulation verification, and hardware experiments to validate the feasibility and effectiveness of the proposed solution.
The remainder of this article is organized as follows. Section 2 discusses the modeling and analysis of leakage current in non-isolated three-phase inverter systems. Section 3 introduces the proposed eleven-switch clamped three-phase photovoltaic inverter, including its operating principles, control strategy, and simulation results. Section 4 describes the hardware circuit design. Section 5 presents the experimental verification and analysis. Finally, Section 6 concludes the article.
2. Modeling and Analysis of Leakage Current in Non-Isolated Three-Phase Inverter Systems
2.1 Parasitic Capacitance and Leakage Current in PV Systems
Photovoltaic modules usually consist of many series- and parallel-connected solar cells encapsulated with a metal frame for mechanical support and grounding. Every solar cell is in close proximity to the metallic frame, forming a parasitic parallel-plate capacitor. In larger PV arrays, the total parasitic capacitance can be quite significant due to the large surface area. Typical values range from 50 to 150 nF/kW for silicon-based PV panels, while thin-film panels can have capacitance values in the range of 1 μF/kW. This parasitic capacitance, when subjected to high-frequency common-mode voltage variations, creates a path for leakage current. Figure 2 in the original dissertation illustrates the basic mechanism, where the PV source, inverter, filters, grid, and parasitic capacitance form a closed loop. In non-isolated inverter systems, because there is no transformer, the high-frequency common-mode voltage directly appears across the parasitic capacitance, causing a common-mode current known as leakage current.
2.2 Standards Related to Leakage Current
Domestic and international standards define the limits for leakage current in non-isolated photovoltaic inverters. According to the Chinese standard NB/T 32004-2013, for inverters with a rated output power less than 30 kVA, the peak leakage current must not exceed 300 mA. For inverters rated above 30 kVA, the leakage current must be less than 10 mA/kVA. The German standard DIN VDE 0126-1-1 requires that if the leakage current exceeds 300 mA, the inverter must disconnect from the grid within 0.3 seconds. In this work, I adopt the 300 mA peak limit as the design target for the proposed inverter.
2.3 Mathematical Model of Common-Mode Voltage and Leakage Current
Figure 2.4 in the original dissertation shows the topology of a conventional three-phase inverter connected to the grid. The common-mode voltage is defined as:
$$u_{cm} = \frac{u_{AQ} + u_{BQ} + u_{CQ}}{3}$$
where \(u_{AQ}, u_{BQ}, u_{CQ}\) are the voltages from the bridge midpoints A, B, C to the negative DC terminal Q. The leakage current path comprises the parasitic capacitance \(C_{PV}\), the filter inductors \(L_a, L_b, L_c\), the grid impedances \(Z_a, Z_b, Z_c\), and the grid voltages \(e_a, e_b, e_c\). After simplifying the model, the leakage current can be expressed as:
$$i_{cm} = \frac{u_{cm}}{j\omega \frac{L}{3} – \frac{1}{\omega C_{PV}}}$$
assuming symmetrical inductors \(L_a = L_b = L_c = L\). The grid voltage frequency is 50 Hz, while the switching frequency is much higher (e.g., 40 kHz). Since the impedance of the grid is small, its contribution to the leakage current is negligible compared with that from the inverter bridge voltages. Therefore, the leakage current is mainly determined by the common-mode voltage and the common-mode loop impedance. The magnitude of the leakage current depends on the amplitude and frequency of the common-mode voltage, the parasitic capacitance, and the filter inductance values.
2.4 Methods to Suppress Leakage Current
Based on the above model, leakage current can be suppressed by several approaches:
1. Reducing the amplitude of the common-mode voltage or maintaining it constant during the switching intervals.
2. Reducing the frequency of the common-mode voltage variations (e.g., using soft-switching techniques).
3. Increasing the impedance of the common-mode loop (e.g., adding common-mode chokes).
4. Using symmetrical layouts and dead-time compensation to avoid parasitic imbalances.
Among these, topology modification and modulation improvements are the most effective methods to minimize the common-mode voltage amplitude. In the next section, I introduce a new topology that clamps the common-mode voltage to specific levels and reduces its variation range.
3. The Eleven-Switch Clamped Three-Phase Photovoltaic Inverter
3.1 Topology and Operating Principles
The proposed eleven-switch clamped three-phase photovoltaic inverter is illustrated in Fig. 3.1 of the original dissertation. It is based on a standard three-phase full-bridge inverter, but adds a freewheeling circuit and a clamping circuit. The freewheeling circuit consists of three freewheeling switches \(S_7, S_8, S_9\) and three diodes \(D_1, D_2, D_3\) connected between the phases: \(D_1\) between A and B, \(D_2\) between B and C, and \(D_3\) between C and A. The freewheeling switches provide a path for the load current when the main bridge switches are turned off. The clamping circuit consists of two series DC-link capacitors \(C_{dc1}\) and \(C_{dc2}\) and two clamping switches \(S_{10}\) and \(S_{11}\). The midpoint of the clamping switches is connected to the neutral point of the DC-link capacitors. When the clamping switches are activated, the common-mode voltage is clamped to half of the DC bus voltage.
The inverter has seven possible operating modes, denoted M1 through M7. Modes M1 through M6 are the active output modes, which correspond to the six non-zero voltage vectors in the conventional three-phase inverter. Mode M7 is the freewheeling mode, in which all six main bridge switches are off, and the freewheeling switches \(S_7, S_8, S_9\) and the clamping switches \(S_{10}, S_{11}\) are on. Table 3.1 in the original dissertation summarizes the switching states and corresponding common-mode voltages. In modes M1, M3, and M5, only one upper switch and two lower switches are on, giving \(u_{cm} = U_{PV}/3\). In modes M2, M4, and M6, two upper switches and one lower switch are on, giving \(u_{cm} = 2U_{PV}/3\). In mode M7, all bridge switches are off, and the clamping action fixes \(u_{cm} = U_{PV}/2\). Therefore, the common-mode voltage never exceeds \(U_{PV}/3\) or \(2U_{PV}/3\), resulting in a variation range of only \(U_{PV}/3\). In contrast, the conventional three-phase inverter has common-mode voltage levels of 0, \(U_{PV}/3\), \(2U_{PV}/3\), and \(U_{PV}\), giving a variation range of \(U_{PV}\). The reduced variation range in the proposed inverter leads to a much lower leakage current.
To illustrate a typical switching sequence, when the inverter transitions from mode M1 to mode M7, the freewheeling switches \(S_7, S_8, S_9\) are turned on before the bridge switches are turned off, and the clamping switches \(S_{10}, S_{11}\) are turned on. The load current continues to flow through the freewheeling path, and the common-mode voltage is clamped to \(U_{PV}/2\). A detailed explanation of each mode is provided below.
| Mode | Conducting switches | \(u_{AQ}\) | \(u_{BQ}\) | \(u_{CQ}\) | \(u_{cm}\) |
|---|---|---|---|---|---|
| M1 | S1,S2,S6,S7 | \(U_{PV}\) | 0 | 0 | \(U_{PV}/3\) |
| M2 | S1,S2,S3,S7,S8 | \(U_{PV}\) | \(U_{PV}\) | 0 | \(2U_{PV}/3\) |
| M3 | S2,S3,S4,S8 | 0 | \(U_{PV}\) | 0 | \(U_{PV}/3\) |
| M4 | S3,S4,S5,S8,S9 | 0 | \(U_{PV}\) | \(U_{PV}\) | \(2U_{PV}/3\) |
| M5 | S4,S5,S6,S9 | 0 | 0 | \(U_{PV}\) | \(U_{PV}/3\) |
| M6 | S1,S5,S6,S7,S9 | \(U_{PV}\) | 0 | \(U_{PV}\) | \(2U_{PV}/3\) |
| M7 | S7,S8,S9,S10,S11 | \(U_{PV}/2\) | \(U_{PV}/2\) | \(U_{PV}/2\) | \(U_{PV}/2\) |
3.2 Control Strategy
For the proposed inverter, I employ a control strategy combining sinusoidal pulse-width modulation (SPWM) with a single voltage closed-loop PI controller and a digital logic module. The overall control block diagram in the original dissertation is shown in Fig. 3.3. The three-phase output voltages \(u_{aN}, u_{bN}, u_{cN}\) are measured and compared with the reference three-phase sinusoidal signals \(u_{ra}, u_{rb}, u_{rc}\). The error signals are processed by PI controllers, whose outputs \(u_{ra}’, u_{rb}’, u_{rc}’\) become the modulation waveforms. These modulation signals are compared with a high-frequency triangular carrier \(u_c\) to generate the logic signals \(X, Y, Z\). Specifically, when \(u_{rx}’ > u_c\), the corresponding signal is set to 1; otherwise, it is 0. The signals \(X, Y, Z\) are then fed to the digital logic module, which generates the eleven gate driving signals \(u_{g1}\) through \(u_{g11}\). The logic expressions are given by:
\[
\begin{aligned}
u_{g1} &= \overline{X}Y + X\overline{Z}, & u_{g4} &= XY + Z, \\
u_{g3} &= \overline{X}Y + Z, & u_{g6} &= \overline{X}Y + \overline{Y}Z, \\
u_{g5} &= XZ + \overline{Y}, & u_{g2} &= XZ + Y, \\
u_{g7} &= X + \overline{Y}Z, & u_{g8} &= Y + \overline{X}Z, \\
u_{g9} &= Z + \overline{X}Y, & u_{g10} &= u_{g11} = \overline{XYZ} + XY.
\end{aligned}
\]
Here, \(Z\) is also used as a variable, and the overbar indicates logical NOT. The logic expressions are implemented using standard logic ICs such as CD4049, CD4071, CD4073, CD4077, and CD4081. The resulting switching sequence ensures that the inverter operates in the desired modes. For example, when \(XYZ = 100\), the inverter operates in mode M1; when \(XYZ = 110\), it operates in mode M2; when \(XYZ = 111\) or \(000\), it operates in the freewheeling mode M7. The gate signals for the freewheeling switches and clamping switches are also generated according to the same logic.
Figure 3.5 in the original dissertation shows the timing relationship between the modulation signals, the carrier, and the gate driving signals for the eleven switches. The common-mode voltage waveform is shown in Fig. 3.6, which resembles a saddle shape, varying between \(U_{PV}/3\) and \(2U_{PV}/3\). This confirms that the common-mode voltage has a low variation range, which is beneficial for leakage current suppression.
3.3 Simulation Results
I built a simulation model in MATLAB/Simulink to validate the proposed topology and control strategy. The simulation parameters are listed in Table 3.3 of the original dissertation: DC input voltage \(U_{PV} = 360\) V, single-phase output voltage (RMS) = 110 V, single-phase rated power = 200 W (total 600 W), DC-link capacitors \(C_{dc1} = C_{dc2} = 220\) μF, filter capacitors \(C_f = 1\) μF, filter inductors \(L = 5\) mH, switching frequency = 40 kHz, parasitic capacitance \(C_{PV} = 100\) nF, rated load resistance \(R = 60\) Ω per phase, and output frequency = 50 Hz. I replaced the photovoltaic panel with a DC regulated power supply in the simulation, and the grid was replaced by a three-phase resistive load because the grid frequency contribution to leakage current is negligible.
Figure 3.7 in the original dissertation shows the SPWM modulation process. The modulation signals are three 50 Hz sinusoidal waves with a phase difference of 120°, and the carrier is a 40 kHz triangular wave. The generated gate signals are shown in Fig. 3.8, which match the theoretical logic. The three-phase bridge voltages \(u_{AQ}, u_{BQ}, u_{CQ}\) and the common-mode voltage \(u_{cm}\) are shown in Fig. 3.9. In mode M7, all three bridge voltages are 180 V (half of 360 V), and \(u_{cm} = 180\) V. In the active modes, the bridge voltages are either 360 V or 0 V, and \(u_{cm}\) takes values of 120 V or 240 V. These results confirm the theoretical analysis.
The output waveforms under full load and half load are shown in Fig. 3.10. The three-phase output voltages have an amplitude of about 154.7 V (RMS 109.1 V) under full load, which is very close to the design value of 110 V. The output current amplitude is 2.58 A under full load, corresponding to an RMS value of 1.82 A. With half load, the voltage remains almost unchanged, while the current is halved. The PI controller effectively maintains the output voltage regardless of the load condition.
To test the dynamic behavior, I simulated load transients. Figure 3.12 in the original dissertation shows the voltage and current waveforms when the load is switched between no-load, half-load, and full-load. The output voltage recovers quickly after each transient, and the voltage remains stable around 110 V RMS. This demonstrates the effectiveness of the closed-loop control.
Leakage current simulations were performed for both the conventional three-phase inverter and the proposed eleven-switch clamped inverter. Figure 3.13 shows the leakage current of the conventional inverter, whose peak value exceeds 300 mA and reaches about 338 mA at the switching frequency. In contrast, Figure 3.14 shows that the proposed inverter has a leakage current peak of approximately 216 mA, and the component at 40 kHz is about 119 mA, which is below the 300 mA limit. The reduction in leakage current is attributed to the reduced common-mode voltage variation range.
4. Hardware Circuit Design
4.1 System Design Specifications
The hardware prototype was designed according to the following specifications: DC input voltage \(U_{PV} = 360\) V ± 10%, single-phase output voltage (RMS) = 110 V, output frequency = 50 Hz, switching frequency = 40 kHz, and single-phase rated power = 200 W. The overall system consists of a power stage and a control stage. The power stage includes the DC input, the eleven-switch clamped topology, and the output LC filters. The control stage includes the reference sine-wave generator, triangle-wave generator, PI controllers, logic circuits, dead-time circuit, and gate-drive circuits.
4.2 Power Stage Component Selection
4.2.1 DC-Link Capacitors
The DC-link capacitors play a critical role in providing a stable midpoint voltage for the clamping circuit. The capacitance value is chosen based on the allowable voltage ripple. Using the formula:
$$C_{dc} \ge \frac{P}{2 \pi f U_{PV}^2 \delta}$$
where \(P = 200\) W per phase, \(f = 50\) Hz, \(U_{PV} = 360\) V, and \(\delta = 3.5\%\), the required total capacitance is 70.7 μF. Since two capacitors are connected in series for the split DC bus, each capacitor must have a capacitance of at least 141.7 μF. To provide a safety margin, I selected two electrolytic capacitors rated at 450 V and 220 μF each.
4.2.2 Power Switches
The power switches must withstand the maximum voltage and current. Due to the high switching frequency (40 kHz), I chose MOSFETs over IGBTs because of their faster switching speed and lower losses. The maximum blocking voltage is 360 V, and considering a 2.5 times safety factor, the devices should be rated at least 900 V. The maximum current through the switches is calculated as follows. The rated RMS output current per phase is:
$$I_{RMS} = \frac{P}{U_{RMS}} = \frac{200}{110} = 1.82 \text{ A}$$
The peak current is 2.57 A. Considering a 1.5 times transient overload and a 20% current ripple, the maximum switch current is:
$$I_{max} = 2.57 \times 1.5 \times 1.2 = 4.63 \text{ A}$$
With a 2 times safety margin, the switches must handle at least 9.26 A. For the gate-drive voltage, the drivers provide 15 V, so a 30 V gate-source rating is sufficient. I selected the MOSFET model MS12N100FC, which has a drain-source breakdown voltage of 1000 V, a continuous drain current of 12 A, an on-resistance of 1.18 Ω, a gate-source voltage rating of ±30 V, and a reverse recovery time below 300 ns. This device meets all requirements.
4.2.3 Freewheeling Diodes
The freewheeling diodes must have a fast reverse recovery time to handle the 40 kHz switching frequency. The maximum reverse voltage across the diodes is 360 V, so with a safety margin, I selected fast-recovery diode US5MC, which has a reverse voltage of 1000 V, a forward current of 5 A, a forward voltage drop of 1.7 V, and a reverse recovery time of 75 ns.
4.2.4 Output LC Filter Design
The output LC filter is used to attenuate the high-frequency switching harmonics. The filter transfer function is:
$$G(s) = \frac{1}{1 + L_f C_f s^2}$$
To achieve at least 40 dB attenuation at the switching frequency (40 kHz), the product \(L_f C_f\) must satisfy:
$$L_f C_f \ge 1.599 \times 10^{-9} \text{ s}^2$$
The filter inductor is chosen based on the current ripple constraint. With a maximum allowable ripple of 20% of the rated current, the minimum inductance is:
$$L_f \ge \frac{U_{PV}}{4 f_s \Delta I_L}$$
Substituting \(U_{PV} = 360\) V, \(f_s = 40\) kHz, and \(\Delta I_L = 0.2 \times 2.57 = 0.514\) A, I obtained \(L_f \ge 4.86\) mH. I chose \(L_f = 5\) mH. For the capacitor, the cutoff frequency of the LC filter should be between 1/20 and 1/10 of the switching frequency, i.e., 2 kHz to 4 kHz. The cutoff frequency is:
$$f_c = \frac{1}{2\pi \sqrt{L_f C_f}}$$
For \(L_f = 5\) mH and \(C_f = 1\) μF, the cutoff frequency is about 2.25 kHz, which is within the acceptable range. The inductor was hand-wound using a PG100-4625 amorphous core. The required number of turns is given by:
$$N = \sqrt{\frac{L}{A_L}}$$
where \(A_L = 0.19 \mu H/N^2\). Thus, \(N \approx 162\) turns. I verified that the magnetic field strength at maximum current is 65 Oe, which is well below the saturation limit of 300 Oe. The inductor wire is rated for 6 A, which is sufficient.
4.3 Control Circuit Design
4.3.1 Reference Three-Phase Sine Wave Generator
The reference sine waves are generated using a crystal oscillator (3.6864 MHz), a CD4060 counter/divider, a CD4018 Johnson counter, a CD40106 Schmitt trigger, and an LF353 operational amplifier. The oscillator is divided to produce a 900 Hz clock, which is further processed by the Johnson counter to generate a 9-level staircase signal. After filtering and amplifying with LF353, the output is a 50 Hz sine wave. Three such circuits are used to produce the three-phase reference signals with 120° phase differences.
4.3.2 Triangle Wave Generator
The triangle wave generator uses two LF353 operational amplifiers configured as a comparator and an integrator. The comparator generates a square wave, which is integrated to produce the triangular waveform. The amplitude and frequency can be adjusted by variable resistors. The output triangle wave is used as the carrier for SPWM modulation.
4.3.3 Digital Logic Module
The digital logic module generates the eleven gate signals based on the logic expressions derived in Section 3.2. It uses the signals \(X, Y, Z\) from the comparators and processes them through logic gates implemented with CD4049, CD4071, CD4073, CD4077, and CD4081. The module outputs the driving signals \(u_{g1}\) through \(u_{g11}\).
4.3.4 Closed-Loop Control Design
The closed-loop control employs PI controllers to regulate the output voltage. The PI controller transfer function is:
$$G_{PI}(s) = \frac{R_f C s + 1}{R C s}$$
The open-loop transfer function of the inverter system is:
$$G(s) = K_{PWM} G_{PI}(s) G_{LC}(s)$$
where \(K_{PWM}\) is the PWM gain, and \(G_{LC}(s)\) is the LC filter transfer function given by:
$$G_{LC}(s) = \frac{R_L}{R_L L C s^2 + L s + R_L}$$
With \(R_L = 60\ \Omega\), \(L = 5\ \text{mH}\), and \(C = 1\ \mu\text{F}\), the open-loop transfer function becomes:
$$G(s) = \frac{12500}{9.375 \times 10^{-11} s^3 + 1.563 \times 10^{-6} s^2 + 1.875 \times 10^{-2} s + 1}$$
I selected the PI parameters as \(R = 30\ \text{k}\Omega\), \(R_f = 40\ \text{k}\Omega\), and \(C = 2\ \text{nF}\). The Routh-Hurwitz criterion and the Nyquist plot show that the system is stable.
4.3.5 Gate Drive Circuit
The gate drive circuit uses the A3120 optocoupler to provide galvanic isolation between the control circuit and the power circuit. The A3120 has a short propagation delay (0.3 μs) and sufficient output current to drive the MOSFETs. The output stage is connected to the gate-source terminals of the switches through a resistor and a diode to reduce oscillations.
4.3.6 Dead-Time Circuit
Dead-time is essential to prevent shoot-through faults in the bridge arms. The dead-time circuit uses an RC delay network with a diode in parallel to provide an asymmetric delay. I set the dead-time to approximately 1 μs, which is enough to ensure safe commutation without significantly distorting the output waveform.
5. Experimental Verification and Analysis
5.1 Hardware Platform
I constructed the hardware prototype based on the designed PCB layouts. The experimental setup includes a Chroma 62050H-600S DC power supply to emulate the PV source, a 100 nF film capacitor to emulate the parasitic capacitance, RXLG aluminum-shell resistors as the load, a Tektronix MDO3024 oscilloscope for waveform measurements, and a FLUKE NORMA-4000N power analyzer for power measurements.
5.2 Control Circuit Results
I measured the gate drive signals for several switches. Figure 5.2 in the original dissertation shows the driving signals for S1, S7, S4, and other switches. The waveforms confirm that S4 and S7 are complementary, and the three-phase signals are shifted by 120°. The dead-time waveform is shown in Fig. 5.3, showing about 1 μs delay between the falling edge and the complementary rising edge, preventing shoot-through.
5.3 Inverter System Results
5.3.1 Bridge Voltage Waveforms
The three-phase bridge voltages \(u_{AQ}, u_{BQ}, u_{CQ}\) are displayed in Fig. 5.4. The measured waveforms have three voltage levels: 360 V, 180 V, and 0 V, which match the simulation results. The common-mode voltage, although not directly measured, can be deduced to have three levels (120 V, 180 V, 240 V) as expected.
5.3.2 Static Test Data
I measured the input and output powers under different load conditions. Table 5.1 in the original dissertation provides the data. The efficiency is around 90-92%, and the output voltage is maintained at approximately 110 V RMS for no-load, half-load, and full-load cases. The output currents are 0 A, 0.92 A, and 1.87 A for the three cases, respectively.
5.3.3 Output Waveforms
Figures 5.5-5.7 show the output voltage and current waveforms under no-load, half-load, and full-load conditions. The three-phase voltages are balanced and sinusoidal with a frequency of 50 Hz. The voltage amplitude remains stable, confirming the correct operation of the closed-loop control.
5.3.4 Load Transient Response
Figure 5.10 shows the response to load transients between no-load, half-load, and full-load. The output voltage experiences a brief transient but recovers to the rated value within about 5 ms. This demonstrates good dynamic performance.
5.3.5 Leakage Current Measurement
I measured the leakage current using a current probe connected to the parasitic capacitance path. The frequency spectrum of the leakage current at full load is shown in Fig. 5.11. The dominant component at 40 kHz is approximately 124 mA, which is below the 300 mA limit. At no-load, the leakage current is about 116 mA. These values are close to the simulation results and confirm the effectiveness of the proposed topology.
6. Conclusion
In this work, I have presented a comprehensive study on an eleven-switch clamped three-phase photovoltaic inverter for leakage current suppression. The proposed topology adds a freewheeling circuit and a clamping circuit to the conventional three-phase inverter, which reduces the common-mode voltage variation range from \(0 \sim U_{PV}\) to \(U_{PV}/3 \sim 2U_{PV}/3\). The control strategy based on SPWM with a single voltage closed-loop PI controller and digital logic has been developed and validated by simulation and experiment. The hardware prototype achieves an output voltage of 110 V RMS per phase with an efficiency above 90%, and the leakage current at the switching frequency is below 300 mA, satisfying the applicable standards. The experimental results are in good agreement with the theoretical analysis and simulation, confirming the correctness and effectiveness of the proposed solution. This work provides a viable approach to addressing the leakage current issue in non-isolated photovoltaic inverters, and I hope it can contribute to the wider adoption of efficient and safe solar energy systems.